Mattela Venkat, Debroy Sanghamitra, Sivasubramani Santhosh, Acharyya Amit
Advanced Embedded Systems and IC Design Laboratory, Department of Electrical Engineering, Indian Institute of Technology, Hyderabad, India.
Nanotechnology. 2021 Feb 26;32(9):095205. doi: 10.1088/1361-6528/abcac9.
In this paper, we propose an interlayer exchange coupling (IEC) based 3D universal NAND/NOR gate design methodology for the reliable and robust implementation of nanomagnetic logic design as compared to the state-of-the art architectures. Owing to stronger coupling scheme as compared to the conventional dipole coupling, the random flip of the states of the nanomagnets (i.e. the soft error) is reduced resulting in greater scalability and better data retention at the deep sub-micron level. Results obtained from Object Oriented Micromagnetic Framework micromagnetic simulation show even at a Curie temperature of the nanomagnets coupled through IEC, the logic function works properly as opposed to dipole coupled nanomagnets which fails at 5 K when scaled down to sub 50 nm. Contemplating the fabrication challenges, the robustness of the IEC design was studied for structural defects, positional misalignment, shape, and size variations. This proposed 3D universal gate design methodology benefits from the miniaturization of nanomagnets as well as reduces the effect of thermally induced errors resulting in opening up a new perspective for nanomagnet based design in magneto-logic devices.
在本文中,我们提出了一种基于层间交换耦合(IEC)的3D通用与非/或非门设计方法,用于实现纳米磁逻辑设计的可靠和稳健性,与现有技术架构相比。由于与传统偶极耦合相比具有更强的耦合方案,纳米磁体状态的随机翻转(即软错误)减少,从而在深亚微米级别实现了更大的可扩展性和更好的数据保持性。从面向对象的微磁框架微磁模拟获得的结果表明,即使在通过IEC耦合的纳米磁体的居里温度下,逻辑功能也能正常工作,而偶极耦合的纳米磁体在缩小到50纳米以下时在5K时就会失效。考虑到制造挑战,研究了IEC设计对于结构缺陷、位置失准、形状和尺寸变化的稳健性。这种提出的3D通用门设计方法受益于纳米磁体的小型化,同时减少了热致误差的影响,为磁逻辑器件中基于纳米磁体的设计开辟了新的前景。