Sui Tengjie, Zhao Zhixiang, Xie Siwei, Xie Yangze, Zhao Yanyan, Huang Qiu, Xu Jianfeng, Peng Qiyu
State Key Laboratory of Digital Manufacturing Equipment and Technology, School of Mechanical Science and Engineering, Huazhong University of Science and Technology, Wuhan 430074, China.
School of Biomedical Engineering, Shanghai Jiaotong University, Shanghai 200240, China.
IEEE Trans Instrum Meas. 2019 Oct;68(10):3647-3660. doi: 10.1109/tim.2018.2880940. Epub 2018 Dec 13.
We present a nonuniform multiphase (NUMP) method to construct a high-resolution time-to-digital converter (TDC) for low-cost field-programmable gate array (FPGA) devices. The NUMP method involves a system clock being passed through a series of delay elements to generate multiple clocks with different phase shifts. The phases of the rising and falling edges of all the clocks are sorted in order and the states of all the clocks are latched when a hit signal arrives. The sizes of the time bins (and precision) of the NUMP method are not limited by the uniformity and minimum value of the time delays of the delay lines. In theory, any delay sources with small jitters in an FPGA, not just very fine carry chains, can be used in the NUMP method to delay and randomize the clocks. Thus, the NUMP method can achieve excellent TDC timing resolutions in low-cost FPGAs without very fine delay lines. We implemented four NUMP TDC channels in a low-cost FPGA device (an Altera Cyclone V 5CEBA4F23C7N). The performance of the four NUMP TDCs was evaluated using both internal and external pulses. The root mean square (rms) for the timing resolution measured using the internal and the external pulses with short-time intervals (less than 1 ns) was 2.3 and 5.2 ps, respectively. A 14.1-ps rms timing resolution was measured at a time interval of 517 ns. The NUMP method is suitable for applications that require a number of high-performance TDC channels in a low-cost FPGA.
我们提出了一种非均匀多相（NUMP）方法，用于为低成本现场可编程门阵列（FPGA）器件构建高分辨率时间数字转换器（TDC）。NUMP方法包括使系统时钟通过一系列延迟元件，以生成具有不同相移的多个时钟。对所有时钟的上升沿和下降沿的相位进行排序，并在命中信号到达时锁存所有时钟的状态。NUMP方法的时间间隔（以及精度）大小不受延迟线时间延迟的均匀性和最小值的限制。理论上，FPGA中任何具有小抖动的延迟源，不仅仅是非常精细的进位链，都可以用于NUMP方法来延迟和随机化时钟。因此，NUMP方法可以在没有非常精细延迟线的低成本FPGA中实现出色的TDC定时分辨率。我们在低成本FPGA器件（Altera Cyclone V 5CEBA4F23C7N）中实现了四个NUMP TDC通道。使用内部和外部脉冲对四个NUMP TDC的性能进行了评估。使用短时间间隔（小于1 ns）的内部和外部脉冲测量的定时分辨率的均方根（rms）分别为2.3和5.2 ps。在517 ns的时间间隔处测量到均方根定时分辨率为14.1 ps。NUMP方法适用于在低成本FPGA中需要多个高性能TDC通道的应用。
