Cui Ke, Li Xiangyu, Zhu Rihong
The MIIT Key Laboratory of Advanced Solid Laser, Nanjing University of Science and Technology, #200 Xiaolingwei, Nanjing, Jiangsu, China.
The School of Computer Science and Engineering, Nanjing University of Science and Technology, #200 Xiaolingwei, Nanjing, Jiangsu, China.
Rev Sci Instrum. 2017 Jun;88(6):064703. doi: 10.1063/1.4985542.
This paper presents an architecture of a high-resolution delay generator implemented in a single field programmable gate array chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in various physical instruments. The proposed delay generator contains the coarse delay step and the fine delay step to guarantee both large dynamic range and high resolution. The carry chains are organized in the Vernier delay loop style to fulfill the fine delay step with high precision and high linearity. The delay generator was implemented in the EP3SE110F1152I3 Stratix III device from Altera on a self-designed test board. Test results show that the obtained resolution is 38.6 ps, and the differential nonlinearity/integral nonlinearity is in the range of [-0.18 least significant bit (LSB), 0.24 LSB]/(-0.02 LSB, 0.01 LSB) under the nominal supply voltage of 1100 mV and environmental temperature of 20 C. The delay generator is rather efficient concerning resource cost, which uses only 668 look-up tables and 146 registers in total.
本文提出了一种通过利用专用进位链的方法在单个现场可编程门阵列芯片中实现的高分辨率延迟发生器架构。它作为各种物理仪器的核心组件。所提出的延迟发生器包含粗延迟步长和细延迟步长，以保证大动态范围和高分辨率。进位链以游标延迟环的方式组织，以高精度和高线性度实现细延迟步长。该延迟发生器在自行设计的测试板上的Altera公司的EP3SE110F1152I3 Stratix III器件中实现。测试结果表明，在1100 mV的标称电源电压和20°C的环境温度下，获得的分辨率为38.6 ps，微分非线性/积分非线性在[-0.18最低有效位（LSB），0.24 LSB]/（-0.02 LSB，0.01 LSB）范围内。该延迟发生器在资源成本方面相当高效，总共仅使用668个查找表和146个寄存器。
