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基于浮栅电压轨迹的二维存储器件的材料与器件结构设计

Material and Device Structure Designs for 2D Memory Devices Based on the Floating Gate Voltage Trajectory.

作者信息

Sasaki Taro, Ueno Keiji, Taniguchi Takashi, Watanabe Kenji, Nishimura Tomonori, Nagashio Kosuke

机构信息

Department of Materials Engineering, The University of Tokyo, Tokyo 113-8656, Japan.

Department of Chemistry, Saitama University, Saitama 338-8570, Japan.

出版信息

ACS Nano. 2021 Apr 27;15(4):6658-6668. doi: 10.1021/acsnano.0c10005. Epub 2021 Mar 25.

DOI:10.1021/acsnano.0c10005
PMID:33765381
Abstract

Two-dimensional heterostructures have been extensively investigated as next-generation nonvolatile memory (NVM) devices. In the past decade, drastic performance improvements and further advanced functionalities have been demonstrated. However, this progress is not sufficiently supported by the understanding of their operations, obscuring the material and device structure design policy. Here, detailed operation mechanisms are elucidated by exploiting the floating gate (FG) voltage measurements. Systematic comparisons of MoTe, WSe, and MoS channel devices revealed that the tunneling behavior between the channel and FG is controlled by three kinds of current-limiting paths, .., tunneling barrier, 2D/metal contact, and p-n junction in the channel. Furthermore, the control experiment indicated that the access region in the device structure is required to achieve 2D channel/FG tunneling by preventing electrode/FG tunneling. The present understanding suggests that the ambipolar 2D-based FG-type NVM device with the access region is suitable for further realizing potentially high electrical reliability.

摘要

二维异质结构作为下一代非易失性存储器(NVM)器件已得到广泛研究。在过去十年中,已展示出显著的性能提升和更先进的功能。然而,对其操作的理解并未充分支持这一进展,模糊了材料和器件结构设计策略。在此,通过利用浮栅(FG)电压测量来阐明详细的操作机制。对MoTe、WSe和MoS沟道器件的系统比较表明,沟道与FG之间的隧穿行为由三种限流路径控制,即隧穿势垒、二维/金属接触和沟道中的p-n结。此外,控制实验表明,器件结构中的访问区域对于通过防止电极/FG隧穿来实现二维沟道/FG隧穿是必需的。目前的理解表明,具有访问区域的基于二维的双极FG型NVM器件适合进一步实现潜在的高电气可靠性。

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