Département d'Optique P. M. Duffieux, Institut FEMTO-ST, Université Bourgogne-Franche-Comté CNRS UMR 6174, Besançon, France; Institute of Physics, Saratov State University, 83 Astrakhanskaya str., 410012 Saratov, Russia.
Département d'Optique P. M. Duffieux, Institut FEMTO-ST, Université Bourgogne-Franche-Comté CNRS UMR 6174, Besançon, France.
Neural Netw. 2022 Feb;146:151-160. doi: 10.1016/j.neunet.2021.11.008. Epub 2021 Nov 13.
Deep neural networks unlocked a vast range of new applications by solving tasks of which many were previously deemed as reserved to higher human intelligence. One of the developments enabling this success was a boost in computing power provided by special purpose hardware, such as graphic or tensor processing units. However, these do not leverage fundamental features of neural networks like parallelism and analog state variables. Instead, they emulate neural networks relying on binary computing, which results in unsustainable energy consumption and comparatively low speed. Fully parallel and analogue hardware promises to overcome these challenges, yet the impact of analogue neuron noise and its propagation, i.e. accumulation, threatens rendering such approaches inept. Here, we determine for the first time the propagation of noise in deep neural networks comprising noisy nonlinear neurons in trained fully connected layers. We study additive and multiplicative as well as correlated and uncorrelated noise, and develop analytical methods that predict the noise level in any layer of symmetric deep neural networks or deep neural networks trained with back propagation. We find that noise accumulation is generally bound, and adding additional network layers does not worsen the signal to noise ratio beyond a limit. Most importantly, noise accumulation can be suppressed entirely when neuron activation functions have a slope smaller than unity. We therefore developed the framework for noise in fully connected deep neural networks implemented in analog systems, and identify criteria allowing engineers to design noise-resilient novel neural network hardware.
深度神经网络通过解决许多以前被认为是人类更高智能所保留的任务,解锁了广泛的新应用。促成这一成功的发展之一是专用硬件(如图形或张量处理单元)提供的计算能力的提高。然而,这些硬件并没有利用神经网络的基本特征,如并行性和模拟状态变量。相反,它们依赖于二进制计算来模拟神经网络,这导致了不可持续的能源消耗和相对较低的速度。完全并行和模拟硬件有望克服这些挑战,但模拟神经元噪声及其传播(即积累)的影响,威胁到使这些方法变得无效。在这里,我们首次确定了在包含经过训练的全连接层中噪声非线性神经元的深度神经网络中噪声的传播。我们研究了加性和乘性噪声,以及相关和不相关噪声,并开发了分析方法,可以预测具有对称深度神经网络或使用反向传播训练的深度神经网络中任何层的噪声水平。我们发现噪声积累通常是有界的,并且在超过一定限制后,添加更多的网络层不会使信噪比恶化。最重要的是,当神经元激活函数的斜率小于 1 时,可以完全抑制噪声积累。因此,我们开发了在模拟系统中实现的全连接深度神经网络中的噪声框架,并确定了允许工程师设计抗噪声新型神经网络硬件的标准。