Xie Jing, Patoary Naim Md, Zhou Guantong, Sayyad Mohammed Yasir, Tongay Sefaattin, Esqueda Ivan Sanchez
Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, 85281, United States of America.
School for Engineering of Matter, Transport & Energy, Arizona State University, Tempe, AZ, 85281, United States of America.
Nanotechnology. 2022 Mar 8;33(22). doi: 10.1088/1361-6528/ac55d2.
Chemical vapor deposition (CVD)-grown monolayer (ML) molybdenum disulfide (MoS) is a promising material for next-generation integrated electronic systems due to its capability of high-throughput synthesis and compatibility with wafer-scale fabrication. Several studies have described the importance of Schottky barriers in analyzing the transport properties and electrical characteristics of MoSfield-effect-transistors (FETs) with metal contacts. However, the analysis is typically limited to single devices constructed from exfoliated flakes and should be verified for large-area fabrication methods. In this paper, CVD-grown ML MoSwas utilized to fabricate large-area (1 cm × 1 cm) FET arrays. Two different types of metal contacts (i.e. Cr/Au and Ti/Au) were used to analyze the temperature-dependent electrical characteristics of ML MoSFETs and their corresponding Schottky barrier characteristics. Statistical analysis provides new insight about the properties of metal contacts on CVD-grown MoScompared to exfoliated samples. Reduced Schottky barrier heights (SBH) are obtained compared to exfoliated flakes, attributed to a defect-induced enhancement in metallization of CVD-grown samples. Moreover, the dependence of SBH on metal work function indicates a reduction in Fermi level pinning compared to exfoliated flakes, moving towards the Schottky-Mott limit. Optical characterization reveals higher defect concentrations in CVD-grown samples supporting a defect-induced metallization enhancement effect consistent with the electrical SBH experiments.
化学气相沉积(CVD)生长的单层(ML)二硫化钼(MoS)因其具有高通量合成能力以及与晶圆级制造的兼容性,是下一代集成电子系统中一种很有前景的材料。几项研究描述了肖特基势垒在分析具有金属接触的MoS场效应晶体管(FET)的传输特性和电学特性方面的重要性。然而,该分析通常仅限于由剥离薄片构建的单个器件,对于大面积制造方法应进行验证。在本文中,利用CVD生长的ML MoS来制造大面积(1 cm×1 cm)的FET阵列。使用两种不同类型的金属接触(即Cr/Au和Ti/Au)来分析ML MoS FET的温度依赖性电学特性及其相应的肖特基势垒特性。统计分析为与剥离样品相比CVD生长的MoS上金属接触的特性提供了新的见解。与剥离薄片相比,获得了降低的肖特基势垒高度(SBH),这归因于CVD生长样品中缺陷诱导的金属化增强。此外,SBH对金属功函数的依赖性表明与剥离薄片相比费米能级钉扎减少,向肖特基-莫特极限发展。光学表征揭示了CVD生长样品中更高的缺陷浓度,支持了与电学SBH实验一致的缺陷诱导金属化增强效应。