• 文献检索
  • 文档翻译
  • 深度研究
  • 学术资讯
  • Suppr Zotero 插件Zotero 插件
  • 邀请有礼
  • 套餐&价格
  • 历史记录
应用&插件
Suppr Zotero 插件Zotero 插件浏览器插件Mac 客户端Windows 客户端微信小程序
定价
高级版会员购买积分包购买API积分包
服务
文献检索文档翻译深度研究API 文档MCP 服务
关于我们
关于 Suppr公司介绍联系我们用户协议隐私条款
关注我们

Suppr 超能文献

核心技术专利:CN118964589B侵权必究
粤ICP备2023148730 号-1Suppr @ 2026

文献检索

告别复杂PubMed语法,用中文像聊天一样搜索,搜遍4000万医学文献。AI智能推荐,让科研检索更轻松。

立即免费搜索

文件翻译

保留排版,准确专业,支持PDF/Word/PPT等文件格式,支持 12+语言互译。

免费翻译文档

深度研究

AI帮你快速写综述,25分钟生成高质量综述,智能提取关键信息,辅助科研写作。

立即免费体验

用于多层MoS晶体管电接触的肖特基势垒高度工程,同时减少金属诱导的能隙态。

Schottky Barrier Height Engineering for Electrical Contacts of Multilayered MoS Transistors with Reduction of Metal-Induced Gap States.

作者信息

Kim Gwang-Sik, Kim Seung-Hwan, Park June, Han Kyu Hyun, Kim Jiyoung, Yu Hyun-Yong

机构信息

School of Electrical Engineering , Korea University , Seoul 02841 , Korea.

Department of Nano Semiconductor Engineering , Korea University , Seoul 02841 , Korea.

出版信息

ACS Nano. 2018 Jun 26;12(6):6292-6300. doi: 10.1021/acsnano.8b03331. Epub 2018 Jun 6.

DOI:10.1021/acsnano.8b03331
PMID:29851473
Abstract

The difficulty in Schottky barrier height (SBH) control arising from Fermi-level pinning (FLP) at electrical contacts is a bottleneck in designing high-performance nanoscale electronics and optoelectronics based on molybdenum disulfide (MoS). For electrical contacts of multilayered MoS, the Fermi level on the metal side is strongly pinned near the conduction-band edge of MoS, which makes most MoS-channel field-effect transistors (MoS FETs) exhibit n-type transfer characteristics regardless of their source/drain (S/D) contact metals. In this work, SBH engineering is conducted to control the SBH of electrical top contacts of multilayered MoS by introducing a metal-interlayer-semiconductor (MIS) structure which induces the Fermi-level unpinning by a reduction of metal-induced gap states (MIGS). An ultrathin titanium dioxide (TiO) interlayer is inserted between the metal contact and the multilayered MoS to alleviate FLP and tune the SBH at the S/D contacts of multilayered MoS FETs. A significant alleviation of FLP is demonstrated as MIS structures with 1 nm thick TiO interlayers are introduced into the S/D contacts. Consequently, the pinning factor ( S) increases from 0.02 for metal-semiconductor (MS) contacts to 0.24 for MIS contacts, and the controllable SBH range is widened from 37 meV (50-87 meV) to 344 meV (107-451 meV). Furthermore, the Fermi-level unpinning effect is reinforced as the interlayer becomes thicker. This work widens the scope for modifying electrical characteristics of contacts by providing a platform to control the SBH through a simple process as well as understanding of the FLP at the electrical top contacts of multilayered MoS.

摘要

在基于二硫化钼(MoS)设计高性能纳米级电子器件和光电器件时,电接触处费米能级钉扎(FLP)导致的肖特基势垒高度(SBH)控制困难是一个瓶颈。对于多层MoS的电接触,金属侧的费米能级强烈钉扎在MoS的导带边缘附近,这使得大多数MoS沟道场效应晶体管(MoS FET)无论其源极/漏极(S/D)接触金属如何,都表现出n型转移特性。在这项工作中,通过引入金属 - 中间层 - 半导体(MIS)结构来进行SBH工程,该结构通过减少金属诱导的能隙态(MIGS)来诱导费米能级去钉扎。在金属接触和多层MoS之间插入超薄二氧化钛(TiO)中间层,以减轻FLP并调节多层MoS FET的S/D接触处的SBH。当将具有1 nm厚TiO中间层的MIS结构引入S/D接触时,FLP得到了显著缓解。因此,钉扎因子(S)从金属 - 半导体(MS)接触的0.02增加到MIS接触的0.24,可控的SBH范围从37 meV(50 - 87 meV)扩大到344 meV(107 - 451 meV)。此外,随着中间层变厚,费米能级去钉扎效应增强。这项工作通过提供一个平台来控制SBH,拓宽了通过简单工艺修改接触电特性的范围,同时也加深了对多层MoS顶部电接触处FLP的理解。

相似文献

1
Schottky Barrier Height Engineering for Electrical Contacts of Multilayered MoS Transistors with Reduction of Metal-Induced Gap States.用于多层MoS晶体管电接触的肖特基势垒高度工程,同时减少金属诱导的能隙态。
ACS Nano. 2018 Jun 26;12(6):6292-6300. doi: 10.1021/acsnano.8b03331. Epub 2018 Jun 6.
2
Schottky Barrier Height Modulation Using Interface Characteristics of MoS Interlayer for Contact Structure.利用 MoS 层间的界面特性调制肖特基势垒高度用于接触结构。
ACS Appl Mater Interfaces. 2019 Feb 13;11(6):6230-6237. doi: 10.1021/acsami.8b18860. Epub 2019 Feb 1.
3
Effective Schottky Barrier Height Lowering of Metal/n-Ge with a TiO/GeO Interlayer Stack.金属/n-Ge 中 TiO/GeO 层叠结构的有效肖特基势垒降低。
ACS Appl Mater Interfaces. 2016 Dec 28;8(51):35419-35425. doi: 10.1021/acsami.6b10947. Epub 2016 Dec 15.
4
Improved Contacts and Device Performance in MoS Transistors Using a 2D Semiconductor Interlayer.使用二维半导体中间层提高金属氧化物半导体场效应晶体管的接触性能和器件性能
ACS Nano. 2020 May 26;14(5):6232-6241. doi: 10.1021/acsnano.0c02303. Epub 2020 May 1.
5
Quasi-Zero-Dimensional Source/Drain Contact for Fermi-Level Unpinning in a Tungsten Diselenide (WSe) Transistor: Approaching Schottky-Mott Limit.用于二硒化钨(WSe)晶体管中费米能级非钉扎的准零维源极/漏极接触:接近肖特基-莫特极限
ACS Nano. 2024 Oct 29;18(43):29771-29778. doi: 10.1021/acsnano.4c09384. Epub 2024 Oct 15.
6
Ultralow Schottky Barrier Height Achieved by Using Molybdenum Disulfide/Dielectric Stack for Source/Drain Contact.采用二硫化钼/介质堆栈实现源/漏接触的超低肖特基势垒高度。
ACS Appl Mater Interfaces. 2019 Sep 18;11(37):34084-34090. doi: 10.1021/acsami.9b10746. Epub 2019 Sep 3.
7
Ambipolar MoS Transistors by Nanoscale Tailoring of Schottky Barrier Using Oxygen Plasma Functionalization.使用氧等离子体功能化纳米尺度调控肖特基势垒实现双极性 MoS 晶体管
ACS Appl Mater Interfaces. 2017 Jul 12;9(27):23164-23174. doi: 10.1021/acsami.7b04919. Epub 2017 Jun 26.
8
Clean Interface Contact Using a ZnO Interlayer for Low-Contact-Resistance MoS Transistors.使用ZnO中间层实现低接触电阻MoS晶体管的清洁界面接触
ACS Appl Mater Interfaces. 2020 Jan 29;12(4):5031-5039. doi: 10.1021/acsami.9b18591. Epub 2020 Jan 13.
9
Junction-Structure-Dependent Schottky Barrier Inhomogeneity and Device Ideality of Monolayer MoS Field-Effect Transistors.单层 MoS 场效应晶体管的结结构相关肖特基势垒非均匀性和器件理想度。
ACS Appl Mater Interfaces. 2017 Mar 29;9(12):11240-11246. doi: 10.1021/acsami.6b16692. Epub 2017 Mar 20.
10
Insertion of an ultrathin AlO interfacial layer for Schottky barrier height reduction in WS field-effect transistors.在 WS 场效应晶体管中插入超薄 AlO 界面层以降低肖特基势垒高度。
Nanoscale. 2019 Mar 14;11(11):4811-4821. doi: 10.1039/c8nr07812b.

引用本文的文献

1
Extension Doping with Low-Resistance Contacts for P-Type Monolayer WSe Field-Effect Transistors.用于P型单层WSe场效应晶体管的具有低电阻接触的外延掺杂
Adv Electron Mater. 2025 Jun;11(9). doi: 10.1002/aelm.202400843. Epub 2024 Dec 8.
2
One-Step Transfer of Symmetric and Asymmetric Contacts for Large-Scale 2D Electronics and Optoelectronics.用于大规模二维电子学和光电子学的对称与非对称接触的一步转移
ACS Nano. 2025 Aug 5;19(30):27919-27929. doi: 10.1021/acsnano.5c09815. Epub 2025 Jul 23.
3
Scalable High-Mobility Graphene/hBN Heterostructures.
可扩展的高迁移率石墨烯/hBN异质结构
ACS Appl Mater Interfaces. 2023 Aug 9;15(31):37794-37801. doi: 10.1021/acsami.3c06120. Epub 2023 Jul 31.
4
Modifying the Power and Performance of 2-Dimensional MoS Field Effect Transistors.二维MoS场效应晶体管的功率与性能调控
Research (Wash D C). 2023;6:0057. doi: 10.34133/research.0057. Epub 2023 Mar 8.
5
Wafer-scale and universal van der Waals metal semiconductor contact.晶圆级和通用的范德华金属半导体接触。
Nat Commun. 2023 Feb 23;14(1):1014. doi: 10.1038/s41467-023-36715-6.
6
Recent Progress in Contact Engineering of Field-Effect Transistor Based on Two-Dimensional Materials.基于二维材料的场效应晶体管接触工程的最新进展
Nanomaterials (Basel). 2022 Oct 31;12(21):3845. doi: 10.3390/nano12213845.
7
Advances of Various Heterogeneous Structure Types in Molecular Junction Systems and Their Charge Transport Properties.各种分子结体系中异质结构类型的进展及其电荷输运性质。
Adv Sci (Weinh). 2022 Oct;9(30):e2202399. doi: 10.1002/advs.202202399. Epub 2022 Aug 17.
8
Effect of AlO Passive Layer on Stability and Doping of MoS Field-Effect Transistor (FET) Biosensors.AlO 无源层对 MoS 场效应晶体管 (FET) 生物传感器稳定性和掺杂的影响。
Biosensors (Basel). 2021 Dec 13;11(12):514. doi: 10.3390/bios11120514.
9
Transferred metal gate to 2D semiconductors for sub-1 V operation and near ideal subthreshold slope.将金属栅极转移至二维半导体以实现低于1V的工作电压和接近理想的亚阈值斜率。
Sci Adv. 2021 Oct 29;7(44):eabf8744. doi: 10.1126/sciadv.abf8744. Epub 2021 Oct 27.
10
On the Contact Optimization of ALD-Based MoS FETs: Correlation of Processing Conditions and Interface Chemistry with Device Electrical Performance.基于原子层沉积的金属氧化物半导体场效应晶体管的接触优化:工艺条件和界面化学与器件电学性能的相关性
ACS Appl Electron Mater. 2021 Jul 27;3(7):3185-3199. doi: 10.1021/acsaelm.1c00379. Epub 2021 Jun 28.