An Jiyong, Oh Seokjin, Nguyen Tien Van, Min Kyeong-Sik
School of Electrical Engineering, Kookmin University, Seoul 02707, Korea.
Micromachines (Basel). 2022 Feb 8;13(2):273. doi: 10.3390/mi13020273.
To overcome the limitations of CMOS digital systems, emerging computing circuits such as memristor crossbars have been investigated as potential candidates for significantly increasing the speed and energy efficiency of next-generation computing systems, which are required for implementing future AI hardware. Unfortunately, manufacturing yield still remains a serious challenge in adopting memristor-based computing systems due to the limitations of immature fabrication technology. To compensate for malfunction of neural networks caused from the fabrication-related defects, a new crossbar training scheme combining the synapse-aware with the neuron-aware together is proposed in this paper, for optimizing the defect map size and the neural network's performance simultaneously. In the proposed scheme, the memristor crossbar's columns are divided into 3 groups, which are the severely-defective, moderately-defective, and normal columns, respectively. Here, each group is trained according to the trade-off relationship between the neural network's performance and the hardware overhead of defect-tolerant training. As a result of this group-based training method combining the neuron-aware with the synapse-aware, in this paper, the new scheme can be successful in improving the network's performance better than both the synapse-aware and the neuron-aware while minimizing its hardware burden. For example, when testing the defect percentage = 10% with MNIST dataset, the proposed scheme outperforms the synapse-aware and the neuron-aware by 3.8% and 3.4% for the number of crossbar's columns trained for synapse defects = 10 and 138 among 310, respectively, while maintaining the smaller memory size than the synapse-aware. When the trained columns = 138, the normalized memory size of the synapse-neuron-aware scheme can be smaller by 3.1% than the synapse-aware.
为了克服CMOS数字系统的局限性，诸如忆阻器交叉开关等新兴计算电路已被作为显著提高下一代计算系统速度和能效的潜在候选者进行研究，这是实现未来人工智能硬件所必需的。不幸的是，由于不成熟制造技术的限制，制造良率在采用基于忆阻器的计算系统方面仍然是一个严峻挑战。为了补偿由制造相关缺陷导致的神经网络故障，本文提出了一种将突触感知与神经元感知相结合的新交叉开关训练方案，以同时优化缺陷映射大小和神经网络性能。在所提出的方案中，忆阻器交叉开关的列被分为3组，分别是严重缺陷列、中度缺陷列和正常列。在此，根据神经网络性能与容错训练硬件开销之间的权衡关系对每组进行训练。作为这种将神经元感知与突触感知相结合的基于组的训练方法的结果，本文提出的新方案能够成功地在最小化硬件负担的同时，比突触感知和神经元感知更好地提高网络性能。例如，在使用MNIST数据集测试缺陷百分比 = 10% 时，对于310列中分别针对突触缺陷训练的交叉开关列数为10和138的情况，所提出的方案在准确率方面分别比突触感知和神经元感知高出3.8%和3.4%，同时保持比突触感知更小的内存大小。当训练列数 = 138时，突触 - 神经元感知方案的归一化内存大小比突触感知小3.1%。
