Nguyen Tien Van, An Jiyong, Min Kyeong-Sik
School of Electrical Engineering, Kookmin University, Seoul 02707, Korea.
Micromachines (Basel). 2021 Jul 1;12(7):791. doi: 10.3390/mi12070791.
Voltages and currents in a memristor crossbar can be significantly affected due to nonideal effects such as parasitic source, line, and neuron resistance. These nonideal effects related to the parasitic resistance can cause the degradation of the neural network's performance realized with the nonideal memristor crossbar. To avoid performance degradation due to the parasitic-resistance-related nonideal effects, adaptive training methods were proposed previously. However, the complicated training algorithm could add a heavy computational burden to the neural network hardware. Especially, the hardware and algorithmic burden can be more serious for edge intelligence applications such as Internet of Things (IoT) sensors. In this paper, a memristor-CMOS hybrid neuron circuit is proposed for compensating the parasitic-resistance-related nonideal effects during not the training phase but the inference one, where the complicated adaptive training is not needed. Moreover, unlike the previous linear correction method performed by the external hardware, the proposed correction circuit can be included in the memristor crossbar to minimize the power and hardware overheads for compensating the nonideal effects. The proposed correction circuit has been verified to be able to restore the degradation of source and output voltages in the nonideal crossbar. For the source voltage, the average percentage error of the uncompensated crossbar is as large as 36.7%. If the correction circuit is used, the percentage error in the source voltage can be reduced from 36.7% to 7.5%. For the output voltage, the average percentage error of the uncompensated crossbar is as large as 65.2%. The correction circuit can improve the percentage error in the output voltage from 65.2% to 8.6%. Almost the percentage error can be reduced to ~1/7 if the correction circuit is used. The nonideal memristor crossbar with the correction circuit has been tested for MNIST and CIFAR-10 datasets in this paper. For MNIST, the uncompensated and compensated crossbars indicate the recognition rate of 90.4% and 95.1%, respectively, compared to 95.5% of the ideal crossbar. For CIFAR-10, the nonideal crossbars without and with the nonideal-effect correction show the rate of 85.3% and 88.1%, respectively, compared to the ideal crossbar achieving the rate as large as 88.9%.
由于寄生源电阻、线路电阻和神经元电阻等非理想效应，忆阻器交叉阵列中的电压和电流会受到显著影响。这些与寄生电阻相关的非理想效应会导致使用非理想忆阻器交叉阵列实现的神经网络性能下降。为了避免由于与寄生电阻相关的非理想效应导致的性能下降，之前提出了自适应训练方法。然而，复杂的训练算法会给神经网络硬件增加沉重的计算负担。特别是，对于物联网（IoT）传感器等边缘智能应用，硬件和算法负担可能会更严重。在本文中，提出了一种忆阻器 - CMOS混合神经元电路，用于在推理阶段而非训练阶段补偿与寄生电阻相关的非理想效应，在此阶段不需要复杂的自适应训练。此外，与之前由外部硬件执行的线性校正方法不同，所提出的校正电路可以包含在忆阻器交叉阵列中，以最小化补偿非理想效应的功耗和硬件开销。所提出的校正电路已被验证能够恢复非理想交叉阵列中源电压和输出电压的下降。对于源电压，未补偿交叉阵列的平均百分比误差高达36.7%。如果使用校正电路，源电压的百分比误差可从36.7%降至7.5%。对于输出电压，未补偿交叉阵列的平均百分比误差高达65.2%。校正电路可将输出电压的百分比误差从65.2%提高到8.6%。如果使用校正电路，几乎百分比误差可降至约1/7。本文针对MNIST和CIFAR - 10数据集测试了带有校正电路的非理想忆阻器交叉阵列。对于MNIST，未补偿和补偿后的交叉阵列的识别率分别为90.4%和95.1%，而理想交叉阵列的识别率为95.5%。对于CIFAR - 10，未进行非理想效应校正和进行了校正的非理想交叉阵列的识别率分别为85.3%和88.1%，而理想交叉阵列的识别率高达88.9%。
