School of Information Science and Technology, Nantong University, Nantong 226019, China.
Sensors (Basel). 2022 Mar 22;22(7):2427. doi: 10.3390/s22072427.
Memory nonlinear error greatly reduces the performance of analog-to-digital converters (ADCs), and this effect is more serious in a time-interleaved analog-to-digital converter (TIADC) system. In this study, the sinusoidal wave fitting method was adopted and a joint error estimation method was proposed to address the memory nonlinear mismatch problem of the current TIADC system. This method divides the nonlinear error estimation method into two steps: the nonlinear mismatch error is coarsely estimated offline using the least squares (LS) method, and then accurately estimated online using the recursive least squares (RLS) method. After the estimation, digital post-compensation method is adopted. The obtained error parameters are used to reconstruct the error and then the reconstructed error is reduced at the output. This study used a four-channel 16-bit TIADC system with an effective number of bits (ENOB) value of 10.06 bits after the introduction of a memory nonlinearity error, which was increased to 15.42 bits after calibration by the joint error estimation method. As a result, the spurious-free dynamic range (SFDR) increased by 36.22 dB. This error estimation method can improve the error estimation accuracy and reduce the hardware complexity of implementing the error estimation system using a field programmable gate array (FPGA).
记忆非线性误差极大地降低了模数转换器 (ADC) 的性能，而这种效应在时间交错模数转换器 (TIADC) 系统中更为严重。在本研究中，采用了正弦波拟合方法，并提出了一种联合误差估计方法来解决当前 TIADC 系统的记忆非线性失配问题。该方法将非线性误差估计方法分为两步：使用最小二乘法 (LS) 离线粗略估计非线性失配误差，然后使用递归最小二乘法 (RLS) 在线精确估计。估计后，采用数字后补偿方法。使用获得的误差参数来重构误差，然后在输出端减小重构误差。本研究使用了一个具有 16 位分辨率的四通道 10.06 位有效位数 (ENOB) 的 TIADC 系统，在引入记忆非线性误差后，通过联合误差估计方法的校准，其有效位数增加到 15.42 位。结果，无杂散动态范围 (SFDR) 提高了 36.22dB。这种误差估计方法可以提高误差估计的准确性，并降低使用现场可编程门阵列 (FPGA) 实现误差估计系统的硬件复杂度。
