Jia Hanbo, Guo Xuan, Zhai Huaiyu, Wu Feitong, Zhang Yuzhen, Wang Dandan, Sun Kai, Wu Danyu, Liu Xinyu
Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China.
University of Chinese Academy of Sciences, Beijing 100049, China.
Micromachines (Basel). 2023 Sep 5;14(9):1738. doi: 10.3390/mi14091738.
As the preferred architecture for high-speed and high-resolution analog-to-digital converters (ADC), the accuracy of pipelined ADC is limited mainly by various errors arising from multiple digital-to-analog converters (MDAC). This paper presents a multi-dimensional (M-D) MDAC calibration based on a genetic algorithm (GA) in a 12-bit 750 MS/s pipelined ADC. The proposed M-D MDAC compensation model enables capacitor mismatch and static interstage gain error (IGE) compensation on the chip and prepares for subsequent background calibration based on a pseudo-random number (PN) injection to achieve accurate compensation for dynamic IGE. An M-D coefficient extraction scheme based on GA is also proposed to extract the required compensation coefficients of the foreground calibration, which avoids falling into local traps through MATLAB. The above calibration scheme has been verified in a prototype 12-bit 750 MS/s pipelined ADC. The measurement results show that the signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are increased from 49.9 dB/66.7 dB to 59.6 dB/77.5 dB with the proposed calibration at 25 °C. With the help of background calibration at 85 °C, the SNDR and SFDR are improved by 3.4 dB and 8.8 dB, respectively.
作为高速和高分辨率模数转换器（ADC）的首选架构，流水线ADC的精度主要受多个数模转换器（MDAC）产生的各种误差限制。本文提出了一种基于遗传算法（GA）的多维（M-D）MDAC校准方法，应用于一款12位750 MS/s的流水线ADC。所提出的M-D MDAC补偿模型能够在芯片上实现电容失配和静态级间增益误差（IGE）补偿，并为后续基于伪随机数（PN）注入的背景校准做准备，以实现对动态IGE的精确补偿。还提出了一种基于GA的M-D系数提取方案，用于提取前景校准所需的补偿系数，通过MATLAB避免陷入局部陷阱。上述校准方案已在一款12位750 MS/s流水线ADC原型中得到验证。测量结果表明，在25°C时，采用所提出的校准方法，信号噪声和失真比（SNDR）和无杂散动态范围（SFDR）分别从49.9 dB/66.7 dB提高到59.6 dB/77.5 dB。在85°C时借助背景校准，SNDR和SFDR分别提高了3.4 dB和8.8 dB。
