Spring Peter A, Cao Shuxiang, Tsunoda Takahiro, Campanaro Giulio, Fasciati Simone, Wills James, Bakr Mustafa, Chidambaram Vivek, Shteynas Boris, Carpenter Lewis, Gow Paul, Gates James, Vlastakis Brian, Leek Peter J
Clarendon Laboratory, Department of Physics, University of Oxford, Oxford OX1 3PU, UK.
Optoelectronics Research Centre, University of Southampton, Southampton SO17 1BJ, UK.
Sci Adv. 2022 Apr 22;8(16):eabl6698. doi: 10.1126/sciadv.abl6698.
We report high qubit coherence as well as low cross-talk and single-qubit gate errors in a superconducting circuit architecture that promises to be tileable to two-dimensional (2D) lattices of qubits. The architecture integrates an inductively shunted cavity enclosure into a design featuring nongalvanic out-of-plane control wiring and qubits and resonators fabricated on opposing sides of a substrate. The proof-of-principle device features four uncoupled transmon qubits and exhibits average energy relaxation times = 149(38) μs, pure echoed dephasing times = 189(34) μs, and single-qubit gate fidelities = 99.982(4)% as measured by simultaneous randomized benchmarking. The 3D integrated nature of the control wiring means that qubits will remain addressable as the architecture is tiled to form larger qubit lattices. Band structure simulations are used to predict that the tiled enclosure will still provide a clean electromagnetic environment to enclosed qubits at arbitrary scale.
我们报告了在一种超导电路架构中实现了高量子比特相干性以及低串扰和单量子比特门错误，这种架构有望扩展为二维（2D）量子比特晶格。该架构将一个电感分流腔封装集成到一种设计中，该设计具有非电平面外控制布线，并且量子比特和谐振器制作在衬底的相对两侧。原理验证器件具有四个非耦合的跨导量子比特，通过同时进行的随机基准测试测量，其平均能量弛豫时间 = 149(38) μs，纯回波退相时间 = 189(34) μs，单量子比特门保真度 = 99.982(4)%。控制布线的三维集成特性意味着，当该架构扩展以形成更大的量子比特晶格时，量子比特仍可寻址。能带结构模拟用于预测，扩展后的封装在任意规模下仍将为封装的量子比特提供纯净的电磁环境。
