He Haibo, Zhao Jianwei, Huang Pengru, Sheng Rongfei, Yu Qiaozhen, He Yuanyuan, Cheng Na
College of Material and Textile Engineering, Key Laboratory of Yarn Materials Forming and Composite Processing Technology, Jiaxing University, Jiaxing 314001, Zhejiang, P. R. China.
School of Material Science & Engineering, Guangxi Key Laboratory of Information Materials and Guangxi Collaborative Innovation Center of Structure and Property for New Energy and Materials, Guilin University of Electronic Technology, Guilin 541004, P. R. China.
Phys Chem Chem Phys. 2022 Sep 14;24(35):21094-21104. doi: 10.1039/d2cp03427a.
Owing to the relatively high carrier mobility and on/off current ratio, monolayered SnS has the advantage of suppressing drain-to-source tunneling for short channels, rendering it a promising candidate in field-effect transistor (FET) applications. To extend the scaling limit of the channel length, we propose to rationally modulate the electronic properties of monolayered SnS through the customized design of point defects and simulate its performance limit in sub-5 nm double-gate FETs (DGFETs), using density functional theory combined with nonequilibrium Green's function formalism. Among all types of point defects, the Se atom as a substitutional dopant (Se) can nondegenerately inject electrons into each monolayered (ML) SnS 2 × 4 × 1 supercell, whereas the Sn vacancy () defect exhibits an opposite doping effect. By adjusting the lateral Schottky barrier height between electrodes and the channel region, the on-state current (), on/off ratio, delay time, and power-delay product in the formed n-type Se-doped SnS and p-type -doped SnS DGFETs with a channel length of 4.5 nm have been remarkably improved, fulfilling the requirements of the International Technology Roadmap for Semiconductors (ITRS) for high-performance applications in the 2028 horizon. Our work unveils the great significance of point defect engineering for applications in ultimately scaled electronics.
由于单层SnS具有相对较高的载流子迁移率和开/关电流比，因此在短沟道情况下具有抑制漏源隧穿的优势，使其成为场效应晶体管（FET）应用中有前景的候选材料。为了扩展沟道长度的缩放极限，我们建议通过定制设计点缺陷来合理调制单层SnS的电子特性，并使用密度泛函理论结合非平衡格林函数形式，模拟其在亚5纳米双栅FET（DGFET）中的性能极限。在所有类型的点缺陷中，作为替代掺杂剂的Se原子（Se）可以非简并地将电子注入到每个单层（ML）SnS 2×4×1超胞中，而Sn空位（）缺陷则表现出相反的掺杂效应。通过调整电极与沟道区域之间的横向肖特基势垒高度，在沟道长度为4.5纳米的形成的n型Se掺杂SnS和p型掺杂SnS DGFET中，导通电流（）、开/关比、延迟时间和功率延迟积都得到了显著改善，满足了国际半导体技术路线图（ITRS）对2028年高性能应用的要求。我们的工作揭示了点缺陷工程在最终缩放电子器件应用中的重大意义。
