Xu Linqiang, Xu Lianqiang, Lan Jun, Li Yida, Li Qiuhui, Wang Aili, Guo Ying, Ang Yee Sin, Quhe Ruge, Lu Jing
State Key Laboratory of Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871, China.
Science, Mathematics and Technology, Singapore University of Technology and Design (SUTD), 8 Somapah Road, Singapore 487372, Singapore.
ACS Appl Mater Interfaces. 2024 May 8;16(18):23536-23543. doi: 10.1021/acsami.4c01353. Epub 2024 Apr 27.
Ultrathin oxide semiconductors are promising candidates for back-end-of-line (BEOL) compatible transistors and monolithic three-dimensional integration. Experimentally, ultrathin indium oxide (InO) field-effect transistors (FETs) with thicknesses down to 0.4 nm exhibit an extremely high drain current (10 μA/μm) and transconductance (4000 μS/μm). Here, we employ ab initio quantum transport simulation to investigate the performance limit of sub-5 nm gate length () ultrathin InO FETs. Based on the International Technology Roadmap for Semiconductors (ITRS) criteria for high-performance (HP) devices, the scaling limit of ultrathin InO FETs can reach 2 nm in terms of on-state current, delay time, and power dissipation. The wide bandgap nature of ultrathin InO (3.0 eV) renders it a suitable candidate for ITRS low-power (LP) electronics with down to 3 nm. Notably, both the HP and LP ultrathin InO FETs exhibit superior energy-delay products as compared to those of other common 2D semiconductors such as monolayer MoS and MoTe. These findings unveil the potential of ultrathin InO in HP and LP nanoelectronic device applications.
超薄氧化物半导体是用于线后端(BEOL)兼容晶体管和单片三维集成的有前途的候选材料。在实验中,厚度低至0.4 nm的超薄氧化铟(InO)场效应晶体管(FET)表现出极高的漏极电流(10 μA/μm)和跨导(4000 μS/μm)。在此,我们采用从头算量子输运模拟来研究亚5 nm栅长()超薄InO FET的性能极限。基于国际半导体技术路线图(ITRS)对高性能(HP)器件的标准,超薄InO FET在导通电流、延迟时间和功耗方面的缩放极限可达到2 nm。超薄InO的宽带隙特性(3.0 eV)使其成为适用于ITRS低功耗(LP)电子器件的候选材料,其栅长可低至3 nm。值得注意的是,与其他常见的二维半导体(如单层MoS和MoTe)相比,HP和LP超薄InO FET均表现出优异的能量延迟积。这些发现揭示了超薄InO在HP和LP纳米电子器件应用中的潜力。