He Yuli, Zheng Guang, Wu Xiaohan, Liu Wen-Jun, Zhang David Wei, Ding Shi-Jin
State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University Shanghai 200433 China
Jiashan Fudan Institute Jiaxing Zhejiang Province 314100 China.
Nanoscale Adv. 2022 Sep 27;4(21):4648-4657. doi: 10.1039/d2na00427e. eCollection 2022 Oct 25.
Thanks to their excellent compatibility with the complementary metal-oxide-semiconductor (CMOS) process, antiferroelectric (AFE) HfO/ZrO-based thin films have emerged as potential candidates for high-performance on-chip energy storage capacitors of miniaturized energy-autonomous systems. However, increasing the energy storage density (ESD) of capacitors has been a great challenge. In this work, we propose the fabrication of ferroelectric (FE) HfZrO/AFE HfZrO bilayer nanofilms by plasma-enhanced atomic layer deposition for high ESD capacitors with TiN electrodes. The effects of the FE/AFE thickness composition and annealing conditions are investigated, revealing that the HfZrO (1 nm)/HfZrO (9 nm) bilayer can generate the optimal ESD after optimized annealing at 450 °C for 30 min. This is mainly ascribed to the factor that the introduction of a 1 nm HfZrO layer enhances the formation of the tetragonal (T) phase with antiferroelectricity in the AFE HfZrO layer as well as the breakdown electric field of the bilayer while fixing the FE/AFE bilayer thickness at 10 nm. As a result, a ESD as high as 71.95 J cm can be obtained together with an energy storage efficiency (ESE) of 57.8%. Meanwhile, with increasing the measurement temperature from 300 and 425 K, the capacitor also demonstrates excellent stabilities of ESD and ESE. In addition, superior electrical cycling endurance is also demonstrated. Further, by integrating the capacitor into deep silicon trenches, a superhigh ESD of 364.1 J cm is achieved together with an ESE of 56.5%. This work provides an effective way for developing CMOS process-compatible, eco-friendly and superhigh ESD three-dimensional capacitors for on-chip energy storage applications.
由于反铁电(AFE)HfO/ZrO基薄膜与互补金属氧化物半导体(CMOS)工艺具有出色的兼容性,已成为小型化能量自主系统高性能片上储能电容器的潜在候选材料。然而,提高电容器的储能密度(ESD)一直是一个巨大的挑战。在这项工作中,我们提出通过等离子体增强原子层沉积制备铁电(FE)HfZrO/AFE HfZrO双层纳米薄膜,用于带有TiN电极的高ESD电容器。研究了FE/AFE厚度组成和退火条件的影响,结果表明,HfZrO(1 nm)/HfZrO(9 nm)双层在450℃优化退火30分钟后可产生最佳ESD。这主要归因于在将FE/AFE双层厚度固定为10 nm的同时,引入1 nm的HfZrO层增强了AFE HfZrO层中具有反铁电性的四方(T)相的形成以及双层的击穿电场。结果,可获得高达71.95 J/cm³的ESD以及57.8%的储能效率(ESE)。同时,随着测量温度从300 K升高到425 K,该电容器还表现出出色的ESD和ESE稳定性。此外,还展示了优异的电循环耐久性。进一步地,通过将该电容器集成到深硅沟槽中,实现了364.1 J/cm³的超高ESD以及56.5%的ESE。这项工作为开发用于片上储能应用的CMOS工艺兼容、环保且超高ESD的三维电容器提供了一种有效方法。