Verma Deeksha, Shehzad Khuram, Kim Sung Jin, Pu Young Gun, Yoo Sang-Sun, Hwang Keum Cheol, Yang Youngoo, Lee Kang-Yoon
Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon 16419, Korea.
SKAIChips Co., Ltd., Suwon 16419, Korea.
Sensors (Basel). 2022 Jul 19;22(14):5393. doi: 10.3390/s22145393.
A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.
采用130nm工艺制造了一种具有片上带隙基准电压发生器的10位1MS/s单端异步逐次逼近寄存器（SAR）模数转换器（ADC）的拟议原型。为了优化功耗、静态和动态性能，提出了几种技术。提出了一种双路径自举开关以提高线性采样。针对电容数模转换器（CDAC）部分采用了基于电压共模（VCM）的电容数模转换器切换技术，以缓解电容性DAC的切换能量问题。所提出的两级动态锁存比较器架构提供了高速和低功耗。此外，为了通过高效的时序实现更快的位转换，实现了具有内部生成时钟的异步SAR逻辑，由于所有转换都在单个时钟周期内进行，因此避免了对高频外部时钟的需求。所提出的基于误差放大器的带隙基准电压发生器为实际应用中的ADC提供了稳定的基准电压。所提出的包括片上带隙基准电压发生器的SAR ADC的测量结果表明，在1.2V电源电压下以1MS/s的采样率工作时，有效位数（ENOB）为9.49位，信噪失真比（SNDR）为58.88dB。
