Department of Materials Engineering, The University of Tokyo, Tokyo, 113-8656, Japan.
Department of Electronics, Nagoya University, Nagoya, 464-8603, Japan.
Small. 2023 Apr;19(15):e2207394. doi: 10.1002/smll.202207394. Epub 2023 Jan 11.
Achieving the direct growth of an ultrathin gate insulator with high uniformity and high quality on monolayer transition metal dichalcogenides (TMDCs) remains a challenge due to the chemically inert surface of TMDCs. Although the main solution for this challenge is utilizing buffer layers before oxide is deposited on the atomic layer, this method drastically degrades the total capacitance of the gate stack. In this work, we constructed a novel direct high-κ Er O deposition system based on thermal evaporation in a differential-pressure-type chamber. A uniform Er O layer with an equivalent oxide thickness of 1.1 nm was achieved as the gate insulator for top-gated MoS field-effect transistors (FETs). The top gate Er O insulator without the buffer layer on MoS exhibited a high dielectric constant that reached 18.0, which is comparable to that of bulk Er O and is the highest among thin insulators (< 10 nm) on TMDCs to date. Furthermore, the Er O /MoS interface (D ≈ 6 × 10 cm eV ) is confirmed to be clean and is comparable with that of the h-BN/MoS heterostructure. These results prove that high-quality dielectric properties with retained interface quality can be achieved by this novel deposition technique, facilitating the future development of 2D electronics.
由于过渡金属二卤族化合物 (TMDCs) 的化学惰性表面,在单层 TMDCs 上实现具有高均匀性和高质量的超薄栅极绝缘层的直接生长仍然是一个挑战。尽管解决这一挑战的主要方法是在原子层沉积氧化物之前利用缓冲层,但这种方法会极大地降低栅堆叠的总电容。在这项工作中,我们构建了一种基于差分压力室热蒸发的新型直接高介电常数 ErO 沉积系统。在顶栅 MoS 场效应晶体管 (FET) 中,作为栅极绝缘体,成功获得了厚度为 1.1nm 的均匀 ErO 层,其等效氧化层厚度为 1.1nm。在没有缓冲层的 MoS 上的顶栅 ErO 绝缘体表现出高介电常数,达到 18.0,与体 ErO 相当,并且是 TMDCs 上所有小于 10nm 的薄膜绝缘体中最高的。此外,确认 ErO/MoS 界面(D ≈ 6×10cm eV)是干净的,与 h-BN/MoS 异质结构相当。这些结果证明,通过这种新型沉积技术可以获得具有保留界面质量的高质量介电性能,从而促进二维电子学的未来发展。