Kim Taehyun, Han Sangwug, Lee Jubum, Na Yeeun, Jung Joontaek, Park Yun Chang, Oh Jaesub, Yang Chungmo, Kim Hee Yeoun
National Nanofab Center, Center of IoT Sensor Development, Daejeon 34141, Republic of Korea.
National Nanofab Center, Center of Analysis and Characterization, Daejeon 34141, Republic of Korea.
Micromachines (Basel). 2023 Feb 14;14(2):448. doi: 10.3390/mi14020448.
Most microsensors are composed of devices and covers. Due to the complicated structure of the cover and various other requirements, it difficult to use wafer-level packaging with such microsensors. In particular, for monolithic microsensors combined with read-out ICs, the available process margins are further reduced due to the thermal and mechanical effects applied to IC wafers during the packaging process. This research proposes a low-temperature, wafer-level vacuum packaging technology based on Cu-Sn bonding and nano-multilayer getter materials for use with microbolometers. In Cu-Sn bonding, the Cu/CuSn/Cu microstructure required to ensure reliability can be obtained by optimizing the bonding temperature, pressure, and time. The Zr-Ti-Ru based nanomultilayer getter coating inside the cap wafer with high step height has been improved by self-aligned shadow masking. The device pad, composed of bonded wafer, was opened by wafer grinding, and the thermoelectrical properties were evaluated at the wafer-level. The bonding strength and vacuum level were characterized by a shear test and thermoelectrical test using microbolometer test pixels. The vacuum level of the packaged samples showed very narrow distribution near 50 mTorr. This wafer-level packaging platform could be very useful for sensor development whereby high reliability and excellent mechanical/optical performance are both required. Due to its reliability and the low material cost and bonding temperature, this wafer-based packaging approach is suitable for commercial applications.
大多数微传感器由器件和覆盖层组成。由于覆盖层结构复杂以及其他各种要求,对这类微传感器采用晶圆级封装很困难。特别是对于与读出集成电路相结合的单片微传感器,由于封装过程中施加在集成电路晶圆上的热效应和机械效应,可用的工艺裕度会进一步降低。本研究提出了一种基于铜锡键合和纳米多层吸气材料的低温晶圆级真空封装技术,用于微测辐射热计。在铜锡键合中,通过优化键合温度、压力和时间,可以获得确保可靠性所需的铜/铜锡/铜微观结构。通过自对准阴影掩膜改进了具有高台阶高度的盖片内部基于锆钛钌的纳米多层吸气涂层。由键合晶圆组成的器件焊盘通过晶圆研磨打开,并在晶圆级评估热电性能。使用微测辐射热计测试像素通过剪切测试和热电测试对键合强度和真空度进行了表征。封装样品的真空度在50毫托附近显示出非常窄的分布。这种晶圆级封装平台对于同时需要高可靠性和优异机械/光学性能的传感器开发可能非常有用。由于其可靠性以及低材料成本和键合温度,这种基于晶圆的封装方法适用于商业应用。