Department of Mechanical Engineering & Mechanics, Drexel University, Philadelphia, Pennsylvania 19104-2875, United States.
State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, P. R. China.
ACS Appl Mater Interfaces. 2023 May 24;15(20):25041-25048. doi: 10.1021/acsami.3c02710. Epub 2023 May 15.
Electric transport in the charged domain wall (CDW) region has emerged as a promising phenomenon for the development of next-generation ferro-resistive memory with ultrahigh data storage density. However, accurately measuring the conductivity of CDWs induced by polarization reversal remains challenging due to the polarization modulation of the Schottky barrier at the thin film-electrode interface, which could partially contribute to the collected "on" current of the device. Here, we propose carefully selecting an electrode that can suppress the effect of interfacial barrier modulation induced by polarization reversal, allowing the collected current mainly from the conductive CDWs. The experiment was conducted on epitaxial BiFeO(001) thin-film devices with vertical and horizontal geometries. Piezo-response force microscopy scanning showed the local polarization experienced 180° rotation to form CDWs under the vertical electric field. However, devices with SrRuO epitaxial top electrodes still exhibit an interfacial barrier-dominated diode behavior, with the "on" current proportional to the electrode area. To identify the CDW current, more interfacial defects were introduced by the deposition of Pt top electrodes, which significantly enhanced charge injection for the compensation of the reversed polarization driven by the electric field, leading to the suppressed polarization modulation of the Schottky barrier height. It was observed that the current flow through Pt electrodes is significantly lower compared to that of SRO electrodes and appears to be primarily influenced by the electrode perimeter instead of the electrode area, indicating CDW-dominated conduction behavior in these devices. Planar nanodevices were further fabricated to support the quantitative investigation of the Pt electrode size-dependent "on" current with a linear fit of the current magnitude versus the CDW cross-sectional area. This work constitutes an essential part of understanding the role of the CDW current in ferro-resistive memory devices.
在带电荷的畴壁（CDW）区域中，电输运现象已经成为开发具有超高数据存储密度的下一代铁电电阻式存储器的一种很有前途的方法。然而，由于薄膜-电极界面处肖特基势垒的极化调制，精确测量由极化反转引起的 CDW 的电导率仍然具有挑战性，这种调制会部分导致器件的“导通”电流。在这里，我们提出仔细选择一个电极，该电极可以抑制由极化反转引起的界面势垒调制的影响，从而使收集到的电流主要来自于导带 CDW。该实验是在具有垂直和水平结构的外延 BiFeO(001) 薄膜器件上进行的。压电响应力显微镜扫描表明，在垂直电场下，局部极化经历 180°旋转形成 CDW。然而，具有 SrRuO 外延顶电极的器件仍然表现出界面势垒主导的二极管行为，“导通”电流与电极面积成正比。为了识别 CDW 电流，通过沉积 Pt 顶电极引入了更多的界面缺陷，这显著增强了电荷注入，以补偿由电场驱动的反转极化，从而抑制了肖特基势垒高度的极化调制。观察到通过 Pt 电极的电流明显低于通过 SRO 电极的电流，并且似乎主要受到电极周长的影响，而不是电极面积的影响，这表明在这些器件中存在 CDW 主导的传导行为。进一步制造了平面纳米器件，以支持对 Pt 电极尺寸依赖性“导通”电流的定量研究，其中电流幅度与 CDW 横截面积呈线性拟合。这项工作是理解 CDW 电流在铁电电阻式存储器器件中作用的重要组成部分。
