Thin Films Laboratory, Department of Physics, Bahauddin Zakariya University, Multan-60800, Pakistan.
Department of Physics, Government College University Faisalabad, Layyah Campus Layyah-31200, Pakistan.
Sci Rep. 2017 Jan 12;7:39539. doi: 10.1038/srep39539.
Resistance switching characteristics of CeO/Ti/CeO tri-layered films sandwiched between Pt bottom electrode and two different top electrodes (Ti and TaN) with different work functions have been investigated. RRAM memory cells composed of TaN/CeO/Ti/CeO/Pt reveal better resistive switching performance instead of Ti/CeO/Ti/CeO/Pt memory stacks. As compared to the Ti/CeO interface, much better ability of TaN/CeO interface to store and exchange plays a key role in the RS performance improvement, including lower forming/SET voltages, large memory window (~10) and no significant data degradation during endurance test of >10 switching cycles. The formation of TaON thinner interfacial layer between TaN TE and CeO film is found to be accountable for improved resistance switching behavior. Partial charge density of states is analyzed using density functional theory. It is found that the conductive filaments formed in CeO based devices is assisted by interstitial Ti dopant. Better stability and reproducibility in cycle-to-cycle (C2C) resistance distribution and V/V uniformity were achieved due to the modulation of current conduction mechanism from Ohmic in low field region to Schottky emission in high field region.
CeO/Ti/CeO 三层薄膜夹在 Pt 底电极和具有不同功函数的两个不同顶电极(Ti 和 TaN)之间的电阻开关特性已经过研究。由 TaN/CeO/Ti/CeO/Pt 组成的 RRAM 存储单元显示出比 Ti/CeO/Ti/CeO/Pt 存储堆叠更好的电阻开关性能。与 Ti/CeO 界面相比,TaN/CeO 界面存储和交换的能力要好得多,这是 RS 性能提高的关键因素,包括更低的形成/SET 电压、更大的存储窗口(~10)以及在>10 次开关循环的耐久性测试中没有明显的数据降级。发现 TaN TE 和 CeO 薄膜之间形成了 TaON 较薄的界面层,这是改善电阻开关行为的原因。使用密度泛函理论分析了部分电荷态密度。发现 CeO 基器件中的导电丝是由间隙 Ti 掺杂剂辅助形成的。由于电流导通机制从低场区域的欧姆到高场区域的肖特基发射的调制,在循环到循环(C2C)电阻分布和 V/V 均匀性方面实现了更好的稳定性和可重复性。