Department of Electrical and Information Technology, Lund University, Box 118, SE-221 00 Lund, Sweden.
NanoLund, Lund University, Box 118, SE-221 00 Lund, Sweden.
Nano Lett. 2023 Jun 14;23(11):4756-4761. doi: 10.1021/acs.nanolett.2c04908. Epub 2023 May 25.
3D integration of III-V semiconductors with Si CMOS is highly attractive since it allows combining new functions such as photonic and analog devices with digital signal processing circuitry. Thus far, most 3D integration approaches have used epitaxial growth on Si, layer transfer by wafer bonding, or die-to-die packaging. Here we present low-temperature integration of InAs on W using SiN template assisted selective area metal-organic vapor-phase epitaxy (MOVPE). Despite growth nucleation on polycrystalline W, we can obtain a high yield of single-crystalline InAs nanowires, as observed by transmission electron microscopy (TEM) and electron backscatter diffraction (EBSD). The nanowires exhibit a mobility of 690 cm/(V s), a low-resistive, Ohmic electrical contact to the W film, and a resistivity which increases with diameter attributed to increased grain boundary scattering. These results demonstrate the feasibility for single-crystalline III-V back-end-of-line integration with a low thermal budget compatible with Si CMOS.
III-V 族半导体与 Si CMOS 的 3D 集成极具吸引力，因为它允许将新功能（如光子和模拟器件）与数字信号处理电路结合在一起。迄今为止，大多数 3D 集成方法都使用 Si 上的外延生长、晶圆键合的层转移或芯片到芯片的封装。在这里，我们使用 SiN 模板辅助选择性区域金属有机气相外延（MOVPE）展示了在 W 上低温集成 InAs。尽管在多晶 W 上发生了生长成核，但我们可以通过透射电子显微镜（TEM）和电子背散射衍射（EBSD）观察到单晶 InAs 纳米线的高产量。这些纳米线表现出 690 cm/（V s）的迁移率、与 W 薄膜的低电阻、欧姆电接触以及电阻率随直径增加而增加，这归因于晶粒边界散射的增加。这些结果表明，与 Si CMOS 兼容的低热预算下进行单晶 III-V 后端集成是可行的。
