Lin Jyi-Tsong, Chang Yen-Chen
Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, 80424, Taiwan, ROC.
Discov Nano. 2023 Aug 5;18(1):99. doi: 10.1186/s11671-023-03878-6.
In this paper, we propose an inductive line tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET). The CEI ETL GS-iTFET allows full overlap between the gate and source regions, thereby enhancing the line tunneling. In addition, a germanium layer is introduced on the source side to form a heterojunction, effectively improving the device's conduction current. An ETL is incorporated to combat point tunneling leakage, resulting in a steeper subthreshold swing. Furthermore, a CEI consisting of SiN is introduced between the germanium source and the Schottky metal, which effectively reduces carrier losses in the inversion layer and improves the overall device performance. This study presents a calibration-based approach to simulations, taking into account practical process considerations. Simulation results show that at V = 0.2 V, the CEI ETL GS-iTFET achieves an average subthreshold swing (SS) of 30.5 mV/dec, an I of 3.12 × 10 A/μm and an I/I ratio of 1.81 × 10. These results demonstrate a significantly low subthreshold swing and a high current ratio of about 10. In addition, the proposed device eliminates the need for multiple implantation processes, resulting in significant manufacturing cost reductions. As a result, the CEI ETL GS-iTFET shows remarkable potential in future low-power device competition.
在本文中，我们提出了一种采用具有锗源和电荷增强绝缘（CEI ETL GS-iTFET）的外延隧道层的电感式线隧穿场效应晶体管。CEI ETL GS-iTFET允许栅极和源极区域完全重叠，从而增强线隧穿。此外，在源极侧引入锗层以形成异质结，有效提高了器件的传导电流。并入一个ETL以对抗点隧穿泄漏，从而获得更陡的亚阈值摆幅。此外，在锗源极和肖特基金属之间引入了由SiN组成的CEI，这有效地减少了反型层中的载流子损耗并提高了整体器件性能。本研究提出了一种基于校准的模拟方法，同时考虑了实际工艺因素。模拟结果表明，在V = 0.2 V时，CEI ETL GS-iTFET的平均亚阈值摆幅（SS）为30.5 mV/dec，I为3.12×10 A/μm，I/I比为1.81×10。这些结果表明亚阈值摆幅极低且电流比约为10。此外，所提出的器件无需多次注入工艺，从而显著降低了制造成本。因此，CEI ETL GS-iTFET在未来低功耗器件竞争中显示出显著的潜力。
