The device performance limit of in-plane monolayer VTe/WTe heterojunction-based field-effect transistors.

To overcome the scaling restriction on silicon-based field-effect transistors (FETs), two-dimensional (2D) transition metal dichalcogenides (TMDs) have been strongly proposed as alternative materials. To explore the device performance limit of TMD-based FETs, in this work, the quantum transport approach is utilized to study the transport properties of monolayer VTe/WTe heterojunction-based FETs possessing double gates (DGs) with a 5 nm gate length (). Our theoretical simulations demonstrate that the DG-cold-source VTe/WTe FETs with a 5 nm and 2 or 3 nm proper underlap () meet the basic requirements of the on-state current (), power dissipation (PDP), and delay time () for the 2028 needs of the International Technology Roadmap for Semiconductor (ITRS) 2013, which ensures their high-performance and low-power-dissipation device applications. Moreover, the DG-cold-source VTe/WTe-based FETs with a 3 nm and 2 or 3 nm meet the high-performance requirements of , , and PDP for the 2028 needs of ITRS 2013. Additionally, by further considering the negative capacitance technology in devices, the parameters , , and PDP of the VTe/WTe-based FETs with a 1 nm and 3 nm meet well with the 2028 needs for ITRS 2013 towards high-performance device applications. Our theoretical results uncover that the 2D DG-cold-source VTe/WTe FETs can be used as a new kind of promising material candidate to drive the scaling of Moore's law down to 1 nm.