Defects Contributing to Hysteresis in Few-Layer and Thin-Film MoS Memristive Devices.

Molybdenum disulfide, a two-dimensional material extensively explored for potential applications in non-von Neumann computing technologies, has garnered significant attention owing to the observed hysteresis phenomena in MoS FETs. The dominant sources of hysteresis reported include charge trapping at the channel-dielectric interface and the adsorption/desorption of molecules. However, in MoS FETs with different channel thicknesses, the specific nature and density of defects contributing to hysteresis remain an intriguing aspect requiring further investigation. This study delves into memristive devices with back-gate modulated channel layers based on CVD-deposited flake-based and thin-film-based MoS FETs, with a few-layer (FL) and thin-film (TF) channel thickness. Analysis of current-voltage (I-V) and conductance-frequency (Gp/ω-f) measurements led to the conclusion that the elevated hysteresis observed in TF MoS devices, as opposed to FL devices, stems from a substantial contribution from intrinsic defects within the channel volume, surpassing that of interface defects. This study underscores the significance of considering both intrinsic defects within the bulk and the interface defects of the channel when analyzing hysteresis in MoS FETs, particularly in TF FETs. The selection between FL and TF MoS devices depends on the requirements for memristive applications, considering factors such as hysteresis tolerance and scaling capabilities.