Zhang Lijun, Dang Wenqiang, Wang Yongshun, Zhang Jinbing
School of Electronic and Information Engineering, Lanzhou Jiaotong University, Lanzhou 730070, China.
School of Electronic Information and Electrical Engineering, Tianshui Normal University, Tianshui 741001, China.
Micromachines (Basel). 2024 Aug 13;15(8):1029. doi: 10.3390/mi15081029.
The key technologies for the ultrathin small outline package (TSOP) of large-sized high-speed chips have been designed and developed in this paper. The designing techniques, such as a 25 µm precise positioning dice attaching technique, a lead frame unit structure without a base island, and a lead co-plane layout inside the frame, were developed. The TSO package outline with a large number of leads, a frame unit arrangement, and a frame distribution with a base island and without one were improved. The technological problems, including the reduction in thickness, wafer cutting, chip sticking bonding, and plastic sealing, were successfully solved. The designed large-sized package products have many advantages, such as high availability, low cost, high reliability, and a short production cycle. This package technique can be widely used in various intellectual application regions.
本文设计并开发了大尺寸高速芯片超薄小外形封装（TSOP）的关键技术。开发了诸如25μm精确定位芯片粘贴技术、无基岛的引线框架单元结构以及框架内引线共面布局等设计技术。改进了具有大量引脚的TSO封装外形、框架单元排列以及有无基岛的框架分布。成功解决了包括厚度减小、晶圆切割、芯片粘贴键合和塑料密封在内的技术问题。所设计的大尺寸封装产品具有高可用性、低成本、高可靠性和短生产周期等诸多优点。这种封装技术可广泛应用于各种智能应用领域。
