Fabrication of Electrospun Porous TiO Dielectric Film in a Ti-TiO-Si Heterostructure for Metal-Insulator-Semiconductor Capacitors.

The development of metal-insulator-semiconductor (MIS) capacitors requires device miniaturization and excellent electrical properties. Traditional SiO gate dielectrics have reached their physical limits. In this context, high-k materials such as TiO are emerging as promising alternatives to SiO. However, the deposition of dielectric layers in MIS capacitors typically requires high-vacuum equipment and challenging processing conditions. Therefore, in this study, we present a new method to effectively fabricate a poly(vinylidene fluoride) (PVDF)-based TiO dielectric layer via electrospinning. Nano-microscale layers were formed via electrospinning by applying a high voltage to a polymer solution, and electrical properties were analyzed as a function of the TiO crystalline phase and residual amount of PVDF at different annealing temperatures. Improved electrical properties were observed with increasing TiO anatase content, and the residual amount of PVDF decreased with increasing annealing temperature. The sample annealed at 600 °C showed a lower leakage current than those annealed at 300 and 450 °C, with a leakage current density of 7.5 × 10 A/cm when Vg = 0 V. Thus, electrospinning-based coating is a cost-effective method to fabricate dielectric thin films. Further studies will show that it is flexible and dielectric tunable, thus contributing to improve the performance of next-generation electronic devices.