Kim Yerim, Noh Hee Yeon, Koo Gyogwon, Lee Hyunki, Lee Sanghan, Choi Rock-Hyun, Lee Shinbuhm, Lee Myoung-Jae, Lee Hyeon-Jun
Division of Nanotechnology, Daegu Gyeongbuk Institute of Science and Technology (DGIST), Daegu 42988, Republic of Korea.
Division of Intelligent Robot, Daegu Gyeongbuk Institute of Science and Technology (DGIST), Daegu 42988, Republic of Korea.
Micromachines (Basel). 2024 Oct 15;15(10):1258. doi: 10.3390/mi15101258.
The development of hardware-based cognitive computing systems critically hinges upon the integration of memristor devices capable of versatile weight expression across a spectrum of resistance levels while preserving consistent electrical properties. This investigation aims to explore the practical implementation of a digit recognition system utilizing memristor devices with minimized weighting levels. Through the process of weight quantization for digits represented by 25 or 49 input signals, the study endeavors to ascertain the feasibility of digit recognition via neural network computation. The integration of memristor devices into the system architecture is poised to streamline the representation of the resistors required for weight expression, thereby facilitating the realization of neural-network-based cognitive systems. To minimize the information corruption in the system caused by weight quantization, we introduce the concept of "weight range" in this work. The weight range is the range between the maximum and minimum values of the weights in the neural network. We found that this has a direct impact on weight quantization, which reduces the number of digits represented by a weight below a certain level. This was found to help maintain the information integrity of the entire system despite the reduction in weight levels. Moreover, to validate the efficacy of the proposed methodology, quantized weights are systematically applied to an array of double-layer neural networks. This validation process involves the construction of cross-point array circuits with dimensions of 25 × 10 and 10 × 10, followed by a meticulous examination of the resultant changes in the recognition rate of randomly generated numbers through device simulations. Such endeavors contribute to advancing the understanding and practical implementation of hardware-based cognitive computing systems leveraging memristor devices and weight quantization techniques.
基于硬件的认知计算系统的发展关键取决于忆阻器设备的集成,这些设备能够在一系列电阻水平上实现通用的权重表达,同时保持一致的电气特性。本研究旨在探索一种利用具有最小化权重水平的忆阻器设备的数字识别系统的实际实现。通过对由25个或49个输入信号表示的数字进行权重量化的过程,该研究致力于确定通过神经网络计算进行数字识别的可行性。将忆阻器设备集成到系统架构中,有望简化权重表达所需电阻器的表示,从而促进基于神经网络的认知系统的实现。为了最小化权重量化在系统中引起的信息损坏,我们在这项工作中引入了“权重范围”的概念。权重范围是神经网络中权重的最大值和最小值之间的范围。我们发现这对权重量化有直接影响,权重量化会减少权重在某一水平以下所表示的数字数量。结果发现,尽管权重水平降低,但这有助于保持整个系统的信息完整性。此外,为了验证所提出方法的有效性,将量化权重系统地应用于一系列双层神经网络。该验证过程包括构建尺寸为25×10和10×10的交叉点阵列电路,然后通过器件模拟仔细检查随机生成数字的识别率的最终变化。这些努力有助于推进对利用忆阻器设备和权重量化技术的基于硬件的认知计算系统的理解和实际实现。