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陷阱辅助隧穿极限下化学气相沉积生长的单层MoS动态随机存取存储器中的阿托安培级泄漏电流。

Attoampere Level Leakage Current in Chemical Vapor Deposition-Grown Monolayer MoS Dynamic Random-Access Memory in Trap-Assisted Tunneling Limit.

作者信息

Seok Jisoo, Seo Jae Eun, Lee Dae Kyu, Kwak Joon Young, Chang Jiwon

机构信息

Center for Neuromorphic Engineering, Korea Institute of Science and Technology, Seoul 02792, Republic of Korea.

Division of Electronic and Semiconductor Engineering, Ewha Womans University, Seoul 03760, Republic of Korea.

出版信息

ACS Nano. 2025 Jan 21;19(2):2458-2467. doi: 10.1021/acsnano.4c13376. Epub 2025 Jan 9.

Abstract

MoS, one of the most researched two-dimensional semiconductor materials, has great potential as the channel material in dynamic random-access memory (DRAM) due to the low leakage current inherited from the atomically thin thickness, high band gap, and heavy effective mass. In this work, we fabricate one-transistor-one-capacitor (1T1C) DRAM using chemical vapor deposition (CVD)-grown monolayer (ML) MoS in large area and confirm the ultralow leakage current of approximately 10 A/μm, significantly lower than the previous report (10 A/μm) in two-transistor-zero-capacitor (2T0C) DRAM based on a few-layer MoS flake. Through rigorous analysis of leakage current considering thermionic emission, tunneling at the source/drain, Shockley-Read-Hall recombination, and trap-assisted tunneling (TAT) current, the TAT current is identified as the primary source of leakage current. These findings highlight the potential of CVD-grown ML MoS to extend the retention time in DRAM and provide a deep understanding of the leakage current sources in MoS 1T1C DRAM for further optimization to minimize the leakage current.

摘要

二硫化钼(MoS)是研究最多的二维半导体材料之一,由于其原子级薄的厚度所带来的低漏电流、高带隙和重有效质量,作为动态随机存取存储器(DRAM)的沟道材料具有巨大潜力。在这项工作中,我们使用化学气相沉积(CVD)生长的大面积单层(ML)MoS制造了单晶体管单电容(1T1C)DRAM,并确认了约10⁻¹¹ A/μm的超低漏电流,显著低于先前基于几层MoS薄片的双晶体管零电容(2T0C)DRAM报告(10⁻⁸ A/μm)。通过考虑热电子发射、源极/漏极处的隧穿、肖克利-里德-霍尔复合以及陷阱辅助隧穿(TAT)电流对漏电流进行严格分析,确定TAT电流是漏电流的主要来源。这些发现突出了CVD生长的ML MoS在延长DRAM保持时间方面的潜力,并为深入理解MoS 1T1C DRAM中的漏电流源以进行进一步优化以最小化漏电流提供了依据。

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