Xiao Kai, Wan Jing, Xie Hui, Zhu Yuxuan, Tian Tian, Zhang Wei, Chen Yingxin, Zhang Jinshu, Zhou Lihui, Dai Sheng, Xu Zihan, Bao Wenzhong, Zhou Peng
School of Information Science and Technology, Fudan University, Shanghai, P. R. China.
State Key Laboratory of ASIC and System, Fudan University, Shanghai, P. R. China.
Nat Commun. 2024 Nov 12;15(1):9782. doi: 10.1038/s41467-024-54218-w.
Embedded Dynamic RAM (eDRAM) has become a key solution for large-capacity cache in high-performance processors. A heterogeneous two transistor capacitorless eDRAM (2T-eDRAM) that combines silicon and molybdenum disulfide (MoS) is reported to address the short retention issue in conventional gain cell (GC) eDRAMs meanwhile eliminate the pillar capacitor in one transistor and one capacitor (1T1C) eDRAMs. The MoS write transistor with low OFF current (I) enables long data retention, while the Si read transistor offers high drive current and logic compatibility. This combination enhances data retention by 1000 times and sense margin by 100 times respectively compared to full Si and MoS counterparts. A three-dimensional (3D) design stacking MoS on Si is demonstrated with back-end-of-line (BEOL) process to double integration density. With 6000 s data retention, 35 μA/μm sense margin, 5 ns access speeds, 3D integration and CMOS logic compatibility, this Si-MoS eDRAM marks a significant advancement in memory technology.
嵌入式动态随机存取存储器（eDRAM）已成为高性能处理器中大容量缓存的关键解决方案。据报道，一种结合了硅和二硫化钼（MoS）的异质双晶体管无电容eDRAM（2T-eDRAM）解决了传统增益单元（GC）eDRAM中数据保持时间短的问题，同时消除了单晶体管单电容（1T1C）eDRAM中的柱形电容。具有低关断电流（I）的MoS写入晶体管可实现长数据保持时间，而Si读取晶体管则提供高驱动电流和逻辑兼容性。与全硅和全MoS同类产品相比，这种组合分别将数据保持能力提高了1000倍，读出裕度提高了100倍。通过后端工艺（BEOL）展示了一种在硅上堆叠MoS的三维（3D）设计，以提高集成密度。这种硅-钼eDRAM具有6000秒的数据保持时间、35μA/μm的读出裕度、5纳秒的访问速度、3D集成和CMOS逻辑兼容性，标志着存储技术取得了重大进展。
