Lee Seungyun, Lee Dongryul, Lee Donggyu, Park Jehwan, Kim Jihyun
Department of Chemical and Biological Engineering, Seoul National University, Seoul 08826, Republic of Korea.
DRAM Process Architecture 2 Group, Samsung Electronics, Yongin-si, Hwaseong 18479, Republic of Korea.
ACS Appl Mater Interfaces. 2025 Apr 30;17(17):25500-25506. doi: 10.1021/acsami.5c02995. Epub 2025 Apr 18.
Si-based electronic devices face inherent performance limitations at the nanoscale, primarily due to short-channel effects and interface defects. As a result, transition-metal dichalcogenides (TMDs) have emerged as promising alternatives, offering unique advantages such as dangling-bond-free surfaces and tunable bandgaps. Among TMDs, tungsten diselenide (WSe) has garnered significant attention as a p-type semiconductor owing to its high hole mobility and favorable surface chemistry. However, its practical implementation is often hindered by Fermi-level pinning at metal contacts, leading to high contact resistance and limited carrier injection efficiency. In this study, we present a mixed-dimensional contact architecture that integrates one-dimensional (1D) edge contacts and two-dimensional (2D) surface contacts to enhance hole injection in WSe field-effect transistors (FETs). By controlling the ratio of the 1D/2D contact architecture, the optimal edge/surface contact ratio from the fabricated WSe FET was obtained when the ratio 1D-length/2D-area = 0.26, exhibiting high field-effect hole mobility (171 cm/V·s) and low specific contact resistance (2.97 kΩ·μm). Ultraviolet/ozone treatment was employed to form tungsten oxide uniformly at the contact regions, facilitating hole doping and thereby reducing contact resistance. The fabricated WSe FETs demonstrated a high current on/off ratio of 5 × 10 and excellent Ohmic contact behavior, with an extracted Schottky barrier height of 0.09 eV. These findings feature the effectiveness of the mixed-dimensional contact architecture in optimizing carrier injection and overcoming the challenges associated with conventional contact schemes. By utilizing the complementary benefits of edge and surface contacts, this approach offers a promising strategy for achieving high-performance TMD-based complementary metal-oxide-semiconductor devices, paving the way for next-generation atomically thin electronic applications.
基于硅的电子器件在纳米尺度上面临固有的性能限制,主要是由于短沟道效应和界面缺陷。因此,过渡金属二硫属化物(TMDs)已成为有前景的替代材料,具有诸如无悬挂键表面和可调节带隙等独特优势。在TMDs中,二硒化钨(WSe)因其高空穴迁移率和良好的表面化学性质而作为p型半导体受到了广泛关注。然而,其实际应用常常受到金属接触处费米能级钉扎的阻碍,导致高接触电阻和有限的载流子注入效率。在本研究中,我们提出了一种混合维度的接触结构,该结构集成了一维(1D)边缘接触和二维(2D)表面接触,以增强WSe场效应晶体管(FETs)中的空穴注入。通过控制1D/2D接触结构的比例,当1D长度/2D面积 = 0.26时,从制备的WSe FET中获得了最佳的边缘/表面接触比例,表现出高场效应空穴迁移率(171 cm²/V·s)和低比接触电阻(2.97 kΩ·μm)。采用紫外/臭氧处理在接触区域均匀形成氧化钨,促进空穴掺杂,从而降低接触电阻。制备的WSe FET表现出5×10⁴的高电流开/关比和优异的欧姆接触行为,提取的肖特基势垒高度为0.09 eV。这些发现突出了混合维度接触结构在优化载流子注入和克服传统接触方案相关挑战方面的有效性。通过利用边缘和表面接触的互补优势,这种方法为实现基于TMD的高性能互补金属氧化物半导体器件提供了一种有前景的策略,为下一代原子级薄电子应用铺平了道路。