Enhancement of On-Current and Reliability in InGaZnO Thin-Film Transistors for Synaptic Circuit Applications through Gate Insulator Stack Engineering.

A nanometer-scale multilayer gate insulator (GI) engineering strategy is introduced to simultaneously enhance the on-current and bias stability of amorphous InGaZnO thin-film transistors (a-IGZO TFTs). Atomic layer deposition supercycle modifications employ alternating layers of AlO, TiO, and SiO to optimize the gate-oxide stack. Each GI material is strategically selected for complementary functionalities: AlO improves the interfacial quality at both the GI/semiconductor and GI/metal interfaces, thereby enhancing device stability and performance; TiO increases the overall dielectric constant; and SiO suppresses leakage current by serving as a high-energy barrier between AlO and TiO. Layer ordering, particularly separating SiO and TiO with AlO, is crucial for suppressing charge trapping and defect-state density, as verified by electrical performance comparisons of the fabricated metal-insulator-metal capacitors and thin-film transistors (TFTs). The optimized multilayer GI demonstrates reduced insulator leakage current, roughly a 1.76× increase in on-current relative to a single-layer AlO GI, a 1.47× mobility increase, and enhanced bias stability with a -5 mV threshold-voltage shift under positive bias stress. Beyond device-level improvements, the cycling endurance of the 6-transistor 1-capacitor synaptic circuit is assessed, demonstrating faster operation and enhanced weight-update cycling stability with the engineered GI compared to conventional designs. This optimization addresses the inherent mobility-reliability trade-off in IGZO TFT fabrication, enabling improved performance for very-large-scale integration circuits and neuromorphic applications.