Synergistic Approaches to Minimize Device Footprint and Energy Consumption in Vertical-Channel Synapse Transistors Using an InGaZnO Active Layer via Spacer Engineering of HfO.

In order to address the limitations of conventional von Neumann architectures in terms of deep neural networks, neuromorphic computing has been proposed as a potential solution. In particular, the emulation of synaptic characteristics represents a significant challenge in the field of high-performance, compact, and energy-efficient device design. From this perspective, a highly effective fabrication engineering approach has been employed to demonstrate 40 nm short-channel vertical synapse thin film transistors (VS-TFTs) that utilize HfO spacer layers, thereby effectively achieving a compact footprint. A channel length of 40 nm was reliably achieved by employing HfO as a spacer material. In addition, the implementation of oxide semiconductor InGaZnO channels and inorganic HfO electrolyte-gated insulators (EGIs) has led to the successful attainment of two primary objectives: low off-state currents and stable device characteristics. In this work, devices employing conventional AlO gate insulators were fabricated, to validate the introduction of the HfO spacer. These devices exhibited a current drivability of 5.6 μA/μm and an on/off ratio of 4.6 × 10, respectively. The VS-TFTs with inorganic HfO EGIs exhibited the successful expression of essential synaptic characteristics, including excitatory/inhibitory postsynaptic currents, paired-pulse facilitation, and long-term plasticity (LTP) through the modulation of the applied pulse conditions. The duration of LTP was defined as 10% of the initial value and was obtained to be 22 s. Linearities were extracted from 50 consecutive potentiation and depression pulses, yielding values of 0.95 and 1.14, respectively. Additionally, the energy consumption measured under specified drain voltage conditions was found to be 1.27 fJ, exhibiting a satisfactory signal-to-noise ratio. This development signifies a substantial advancement for neuromorphic hardware systems.