Oya Takahide, Asai Tetsuya, Fukui Takashi, Amemiya Yoshihito
Department of Electrical Engineering, Hokkaido University, Sapporo 060-8628, Japan.
J Nanosci Nanotechnol. 2002 Jun-Aug;2(3-4):333-42. doi: 10.1166/jnn.2002.108.
This paper describes a majority-logic gate device that will be useful in developing single-electron integrated circuits. The gate device consists of two identical single-electron boxes combined to form a balanced pair. It accepts three inputs and produces a majority-logic output by using imbalances caused by the input signals; it produces a 1 output if two or three inputs are 1, and a 0 output if two or three inputs are 0. We combine these gate devices into two subsystems, a shift register and an adder, and demonstrate their operation by computer simulation. We also propose a method of fabricating the unit element of the gate device, a minute dot with four coupling arms. We demonstrate by experiments that it is possible to arrange these unit elements on a GaAs substrate, in a self-organizing manner, by means of a process technology that is based on selective-area metalorganic vapor-phase epitaxy.
本文描述了一种多数逻辑门器件，它在开发单电子集成电路方面将很有用。该门器件由两个相同的单电子盒组合而成，形成一个平衡对。它接受三个输入，并利用输入信号引起的不平衡产生多数逻辑输出；如果两个或三个输入为1，则产生1输出，如果两个或三个输入为0，则产生0输出。我们将这些门器件组合成两个子系统，一个移位寄存器和一个加法器，并通过计算机模拟演示它们的操作。我们还提出了一种制造门器件单元元件的方法，即带有四个耦合臂的微小点。我们通过实验证明，借助基于选择性区域金属有机气相外延的工艺技术，可以在砷化镓衬底上以自组织方式排列这些单元元件。
