Al-Alawi Raida
Department of Electrical and Electronic Engineering, University of Bahrain, PO Box 32038, Bahrain.
Int J Neural Syst. 2003 Aug;13(4):225-37. doi: 10.1142/S012906570300156X.
A hardware architecture of a Probabilistic Logic Neuron (PLN) is presented. The suggested model facilitates the on-chip learning of pyramidal Weightless Neural Networks using a modified probabilistic search reward/penalty training algorithm. The penalization strategy of the training algorithm depends on a predefined parameter called the probabilistic search interval. A complete Weightless Neural Network (WNN) learning system is modeled and implemented on Xilinx XC4005E Field Programmable Gate Array (FPGA), allowing its architecture to be configurable. Various experiments have been conducted to examine the feasibility and performance of the WNN learning system. Results show that the system has a fast convergence rate and good generalization ability.
提出了一种概率逻辑神经元（PLN）的硬件架构。所建议的模型使用改进的概率搜索奖励/惩罚训练算法促进了金字塔型无权重神经网络的片上学习。训练算法的惩罚策略取决于一个称为概率搜索间隔的预定义参数。一个完整的无权重神经网络（WNN）学习系统在Xilinx XC4005E现场可编程门阵列（FPGA）上进行了建模和实现，使其架构具有可配置性。已经进行了各种实验来检验WNN学习系统的可行性和性能。结果表明，该系统具有快速的收敛速度和良好的泛化能力。
