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关于双重任务干扰的位置:刺激分类阶段是否存在瓶颈?

On the locus of dual-task interference: Is there a bottleneck at the stimulus classification stage?

作者信息

Johnston James C, McCann Robert S

机构信息

NASA Ames Research Center, MS 262-4, Moffett Field, CA 94035, USA.

出版信息

Q J Exp Psychol (Hove). 2006 Apr;59(4):694-719. doi: 10.1080/02724980543000015.

DOI:10.1080/02724980543000015
PMID:16707358
Abstract

Recent studies have provided evidence that dual-task interference is typically caused by a single-channel bottleneck, but the processing locus of the bottleneck has yet to be pinned down. A bottleneck locus at the response-selection stage is widely advocated, but an earlier locus would be consistent with most previous evidence. Four new experiments used the "locus of slack" method to investigate whether the stages postponed by the central bottleneck include stimulus classification, a very late stage of perceptual processing. The experiments varied stimulus classification difficulty for two different analogueue perceptual judgements. Experiment 1 found only modest absorption into slack for the difficulty of a spatial position judgement. Experiments 2-4 found virtually no absorption into slack for the difficulty of a box-width judgement. These results support a bottleneck locus beginning at or before the stage of stimulus classification and hence prior to the stage of response selection. Other evidence, however, leaves no doubt that response selection is also subject to bottleneck postponement. Two architectures are discussed that can account parsimoniously for both old and new results. One posits a single bottleneck resulting from a unified CPU-like central processor; the other posits multiple bottlenecks resulting from multiple processors accomplishing different substages of central processing.

摘要

近期研究已提供证据表明,双重任务干扰通常由单通道瓶颈导致,但该瓶颈的处理位点尚未确定。反应选择阶段的瓶颈位点受到广泛支持,但更早的位点会与大多数先前证据相符。四项新实验采用“松弛位点”方法来探究由中央瓶颈延迟的阶段是否包括刺激分类,这是感知处理的一个非常后期的阶段。实验针对两种不同的类似感知判断改变了刺激分类难度。实验1发现,对于空间位置判断的难度,仅有适度的松弛吸收。实验2至4发现,对于盒宽判断的难度,几乎没有松弛吸收。这些结果支持瓶颈位点始于刺激分类阶段或之前,因此在反应选择阶段之前。然而,其他证据明确表明反应选择也会受到瓶颈延迟的影响。讨论了两种架构,它们能够简洁地解释新旧结果。一种架构假定由类似统一CPU的中央处理器导致单一瓶颈;另一种架构假定由完成中央处理不同子阶段的多个处理器导致多个瓶颈。

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