Ryu Koungmin, Badmaev Alexander, Wang Chuan, Lin Albert, Patil Nishant, Gomez Lewis, Kumar Akshay, Mitra Subhasish, Wong H-S Philip, Zhou Chongwu
Department of Electrical Engineering, University of Southern California, Los Angeles, California 90089, USA.
Nano Lett. 2009 Jan;9(1):189-97. doi: 10.1021/nl802756u.
Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.
大规模排列的碳纳米管具有巨大潜力，但在未来超越硅的纳米电子学中也面临重大的集成/组装挑战。我们报道了一种排列纳米管器件和集成电路的晶圆级加工方法，包括在关键技术组件方面取得的进展，如排列纳米管的晶圆级合成、纳米管向硅晶圆的晶圆级转移、金属纳米管去除和化学掺杂，以及容错集成纳米管电路。我们已经在完整的4英寸石英和蓝宝石衬底上实现了大规模排列纳米管的合成，然后将其转移到4英寸的Si/SiO₂晶圆上。采用互补金属氧化物半导体（CMOS）类似的制造工艺来制造特征尺寸低至0.5微米的晶体管和电路，具有约20微安/微米的高电流密度和良好的开/关比。此外，化学掺杂已被用于构建增益约为5的全集成互补反相器，并且对与非门和或非门采用了容错设计。这种全晶圆方法可为未来的集成纳米管电路奠定关键基础。
