Okcan Burak, Merken Patrick, Gielen Georges, Van Hoof Chris
IMEC, Kapeldreef 75, B-3001 Leuven, Belgium.
Rev Sci Instrum. 2010 Feb;81(2):024702. doi: 10.1063/1.3309825.
This paper presents a cryogenic successive approximation register (SAR) based analog to digital converter (ADC) implemented in a standard 0.35 microm complementary metal oxide semiconductor (CMOS) process. It operates from room temperature down to 4.4 K, achieving 10.47 effective number of bits (ENOB) at room temperature. At 4.4 K, the ADC achieves 8.53 ENOB at 50 kS/s sampling rate with a current consumption of 90 microA from a 3.3 V supply. The ADC utilizes an improved comparator architecture, which performs offset cancellation by using preamplifiers designed for cryogenic operation. The conventional offset cancellation algorithm is also modified in order to eliminate the effect of cryogenic anomalies below freeze-out temperature. The power efficiency is significantly improved compared to the state of the art semiconductor ADCs operating in the same temperature range.
本文介绍了一种基于低温逐次逼近寄存器（SAR）的模数转换器（ADC），该转换器采用标准的0.35微米互补金属氧化物半导体（CMOS）工艺实现。它能在室温至4.4 K的温度范围内工作，在室温下实现了10.47有效位数（ENOB）。在4.4 K时，该ADC在50 kS/s采样率下实现了8.53 ENOB，从3.3 V电源汲取的电流为90 μA。该ADC采用了改进的比较器架构，通过使用专为低温操作设计的前置放大器来执行失调消除。传统的失调消除算法也进行了修改，以消除低于冻结温度的低温异常影响。与在相同温度范围内工作的现有半导体ADC相比，其功率效率得到了显著提高。
