Institute of Microelectronics, Chinese Academy of Sciences, Beijing, People's Republic of China.
Nanotechnology. 2011 Jun 24;22(25):254009. doi: 10.1088/0957-4484/22/25/254009. Epub 2011 May 16.
The endurance of Si nanocrystal memory devices under Fowler-Nordheim program and erase (P/E) cycling is investigated. Both threshold voltage (V(th)) and subthreshold swing (SS) degradation are observed when using a high program or erase voltage. The change of SS is found to be proportional to the shift of V(th), indicating that the generation of interface traps plays a dominant role. The charge pumping and the mid-gap voltage methods have been used to analyze endurance degradation both qualitatively and quantitatively. It is concluded that high erase voltage causes severe threshold voltage degradation by generating more interface traps and trapped oxide charges.
研究了在福勒-诺德海姆编程和擦除（P/E）循环下 Si 纳米晶存储器的耐久性。当使用高编程或擦除电压时，观察到阈值电压（V（th））和亚阈值摆幅（SS）的退化。发现 SS 的变化与 V（th）的偏移成正比，表明界面陷阱的产生起主导作用。电荷泵和中间隙电压方法已用于定性和定量地分析耐久性退化。结论是，高擦除电压通过产生更多的界面陷阱和俘获氧化物电荷，导致严重的阈值电压退化。
