• 文献检索
  • 文档翻译
  • 深度研究
  • 学术资讯
  • Suppr Zotero 插件Zotero 插件
  • 邀请有礼
  • 套餐&价格
  • 历史记录
应用&插件
Suppr Zotero 插件Zotero 插件浏览器插件Mac 客户端Windows 客户端微信小程序
定价
高级版会员购买积分包购买API积分包
服务
文献检索文档翻译深度研究API 文档MCP 服务
关于我们
关于 Suppr公司介绍联系我们用户协议隐私条款
关注我们

Suppr 超能文献

核心技术专利:CN118964589B侵权必究
粤ICP备2023148730 号-1Suppr @ 2026

文献检索

告别复杂PubMed语法,用中文像聊天一样搜索,搜遍4000万医学文献。AI智能推荐,让科研检索更轻松。

立即免费搜索

文件翻译

保留排版,准确专业,支持PDF/Word/PPT等文件格式,支持 12+语言互译。

免费翻译文档

深度研究

AI帮你快速写综述,25分钟生成高质量综述,智能提取关键信息,辅助科研写作。

立即免费体验

VLSI 电路实现新皮层电路的计算模型。

VLSI circuits implementing computational models of neocortical circuits.

机构信息

The University of Manchester, United Kingdom.

出版信息

J Neurosci Methods. 2012 Sep 15;210(1):93-109. doi: 10.1016/j.jneumeth.2012.01.019. Epub 2012 Feb 11.

DOI:10.1016/j.jneumeth.2012.01.019
PMID:22342970
Abstract

This paper overviews the design and implementation of three neuromorphic integrated circuits developed for the COLAMN ("Novel Computing Architecture for Cognitive Systems based on the Laminar Microcircuitry of the Neocortex") project. The circuits are implemented in a standard 0.35 μm CMOS technology and include spiking and bursting neuron models, and synapses with short-term (facilitating/depressing) and long-term (STDP and dopamine-modulated STDP) dynamics. They enable execution of complex nonlinear models in accelerated-time, as compared with biology, and with low power consumption. The neural dynamics are implemented using analogue circuit techniques, with digital asynchronous event-based input and output. The circuits provide configurable hardware blocks that can be used to simulate a variety of neural networks. The paper presents experimental results obtained from the fabricated devices, and discusses the advantages and disadvantages of the analogue circuit approach to computational neural modelling.

摘要

本文概述了为 COLAMN(“基于新皮质层状微电路的认知系统的新型计算架构”)项目开发的三个神经形态集成电路的设计和实现。这些电路是在标准的 0.35 μm CMOS 技术中实现的,包括尖峰和突发神经元模型,以及具有短期(促进/抑制)和长期(STDP 和多巴胺调制 STDP)动力学的突触。与生物学相比,它们能够以加速的时间执行复杂的非线性模型,并且功耗低。神经动力学使用模拟电路技术实现,具有数字异步基于事件的输入和输出。这些电路提供可配置的硬件模块,可用于模拟各种神经网络。本文介绍了从制造的设备中获得的实验结果,并讨论了模拟电路方法在计算神经建模中的优缺点。

相似文献

1
VLSI circuits implementing computational models of neocortical circuits.VLSI 电路实现新皮层电路的计算模型。
J Neurosci Methods. 2012 Sep 15;210(1):93-109. doi: 10.1016/j.jneumeth.2012.01.019. Epub 2012 Feb 11.
2
A forecast-based STDP rule suitable for neuromorphic implementation.一种适用于神经形态实现的基于预测的 STDP 规则。
Neural Netw. 2012 Aug;32:3-14. doi: 10.1016/j.neunet.2012.02.018. Epub 2012 Feb 14.
3
Computing with networks of spiking neurons on a biophysically motivated floating-gate based neuromorphic integrated circuit.基于生物启发的浮栅的神经形态集成电路的尖峰神经元网络的计算。
Neural Netw. 2013 Sep;45:39-49. doi: 10.1016/j.neunet.2013.02.011. Epub 2013 Mar 7.
4
Self-tuning of neural circuits through short-term synaptic plasticity.通过短期突触可塑性实现神经回路的自我调节。
J Neurophysiol. 2007 Jun;97(6):4079-95. doi: 10.1152/jn.01357.2006. Epub 2007 Apr 4.
5
Analog-digital simulations of full conductance-based networks of spiking neurons with spike timing dependent plasticity.基于全电导的具有脉冲时间依赖可塑性的脉冲神经元网络的模拟数字仿真。
Network. 2006 Sep;17(3):211-33. doi: 10.1080/09548980600711124.
6
A neuromorphic VLSI design for spike timing and rate based synaptic plasticity.一种基于尖峰时间和比率的神经形态 VLSI 设计用于突触可塑性。
Neural Netw. 2013 Sep;45:70-82. doi: 10.1016/j.neunet.2013.03.003. Epub 2013 Mar 15.
7
Design of silicon brains in the nano-CMOS era: spiking neurons, learning synapses and neural architecture optimization.纳米 CMOS 时代的硅脑设计:尖峰神经元、学习突触和神经架构优化。
Neural Netw. 2013 Sep;45:4-26. doi: 10.1016/j.neunet.2013.05.011. Epub 2013 Jun 6.
8
PAX: A mixed hardware/software simulation platform for spiking neural networks.PAX:用于尖峰神经网络的混合硬件/软件模拟平台。
Neural Netw. 2010 Sep;23(7):905-16. doi: 10.1016/j.neunet.2010.02.006. Epub 2010 Apr 2.
9
Chaos-based mixed signal implementation of spiking neurons.基于混沌的尖峰神经元混合信号实现。
Int J Neural Syst. 2009 Dec;19(6):465-71. doi: 10.1142/S0129065709002166.
10
What can a neuron learn with spike-timing-dependent plasticity?神经元通过尖峰时间依赖性可塑性能够学习什么?
Neural Comput. 2005 Nov;17(11):2337-82. doi: 10.1162/0899766054796888.

引用本文的文献

1
A Neuromorphic Digital Circuit for Neuronal Information Encoding Using Astrocytic Calcium Oscillations.一种利用星形胶质细胞钙振荡进行神经元信息编码的神经形态数字电路。
Front Neurosci. 2019 Oct 9;13:998. doi: 10.3389/fnins.2019.00998. eCollection 2019.
2
Neuromorphic Implementation of Attractor Dynamics in a Two-Variable Winner-Take-All Circuit with NMDARs: A Simulation Study.具有NMDAR的双变量胜者全得电路中吸引子动力学的神经形态实现:一项模拟研究。
Front Neurosci. 2017 Feb 7;11:40. doi: 10.3389/fnins.2017.00040. eCollection 2017.
3
Generalized reconfigurable memristive dynamical system (MDS) for neuromorphic applications.
用于神经形态应用的广义可重构忆阻动态系统(MDS)。
Front Neurosci. 2015 Nov 3;9:409. doi: 10.3389/fnins.2015.00409. eCollection 2015.
4
PyNCS: a microkernel for high-level definition and configuration of neuromorphic electronic systems.PyNCS:用于神经形态电子系统高级定义和配置的微内核。
Front Neuroinform. 2014 Aug 29;8:73. doi: 10.3389/fninf.2014.00073. eCollection 2014.
5
Tunable low energy, compact and high performance neuromorphic circuit for spike-based synaptic plasticity.用于基于脉冲的突触可塑性的可调谐低能量、紧凑型高性能神经形态电路。
PLoS One. 2014 Feb 13;9(2):e88326. doi: 10.1371/journal.pone.0088326. eCollection 2014.