Choi Sungjin, Lee Junhyuk, Kim Donghyoun, Oh Seulki, Song Wangyu, Choi Seonjun, Choi Eunsuk, Lee Seung-Beck
Department of Nanoscale Semiconductor Engineering, Hanyang University, 17 Haengdangdong, Seongdonggu, Seoul 133-791, Korea.
J Nanosci Nanotechnol. 2011 Dec;11(12):10553-6. doi: 10.1166/jnn.2011.4009.
We report on the fabrication and capacitance-voltage characteristics of double layer nickel-silicide nanocrystals with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO2 interlayer, the use of Si3N4 interlayer separation reduced the average size (4 nm) and distribution (+/- 2.5 nm) of NiSi2 nanocrystal (NC) charge traps by more than 50% and giving a two fold increase in NC density to 2.3 x 10(12) cm(-2). The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C-V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50% on average to less than 0.7 V demonstrating possible multi-level-cell operation.
