Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, United States.
ACS Nano. 2012 Apr 24;6(4):3121-7. doi: 10.1021/nn3008788. Epub 2012 Apr 5.
We investigate the bias-stress effect in field-effect transistors (FETs) consisting of 1,2-ethanedithiol-treated PbS quantum dot (QD) films as charge transport layers in a top-gated configuration. The FETs exhibit ambipolar operation with typical mobilities on the order of μ(e) = 8 × 10(-3) cm(2) V(-1) s(-1) in n-channel operation and μ(h) = 1 × 10(-3) cm(2) V(-1) s(-1) in p-channel operation. When the FET is turned on in n-channel or p-channel mode, the established drain-source current rapidly decreases from its initial magnitude in a stretched exponential decay, manifesting the bias-stress effect. The choice of dielectric is found to have little effect on the characteristics of this bias-stress effect, leading us to conclude that the associated charge-trapping process originates within the QD film itself. Measurements of bias-stress-induced time-dependent decays in the drain-source current (I(DS)) are well fit to stretched exponential functions, and the time constants of these decays in n-channel and p-channel operation are found to follow thermally activated (Arrhenius) behavior. Measurements as a function of QD size reveal that the stressing process in n-channel operation is faster for QDs of a smaller diameter while stress in p-channel operation is found to be relatively invariant to QD size. Our results are consistent with a mechanism in which field-induced nanoscale morphological changes within the QD film result in screening of the applied gate field. This phenomenon is entirely recoverable, which allows us to repeatedly observe bias stress and recovery characteristics on the same device. This work elucidates aspects of charge transport in chemically treated lead chalcogenide QD films and is of relevance to ongoing investigations toward employing these films in optoelectronic devices.
我们研究了场效应晶体管（FET）中的偏置-应力效应，这些 FET 由经过 1,2-乙二硫醇处理的 PbS 量子点（QD）薄膜作为电荷输运层，采用顶栅结构。FET 表现出双极性操作，典型的迁移率在 n 通道操作中约为 μ(e) = 8 × 10(-3) cm(2) V(-1) s(-1)，在 p 通道操作中约为 μ(h) = 1 × 10(-3) cm(2) V(-1) s(-1)。当 FET 在 n 通道或 p 通道模式下导通时，建立的漏源电流会迅速从其初始值以拉伸指数衰减的形式减小，表现出偏置-应力效应。我们发现，选择介电常数对这种偏置-应力效应的特性影响不大，这导致我们得出结论，相关的电荷俘获过程起源于 QD 薄膜本身。对漏源电流（I(DS)）的偏置-应力诱导的时变衰减的测量很好地符合拉伸指数函数，并且在 n 通道和 p 通道操作中这些衰减的时间常数遵循热激活（Arrhenius）行为。对 QD 尺寸的测量表明，在 n 通道操作中，较小直径的 QD 的应力过程更快，而在 p 通道操作中，应力相对不受 QD 尺寸的影响。我们的结果与一种机制一致，即 QD 薄膜内的电场诱导纳米级形态变化导致施加栅极场的屏蔽。这种现象是完全可恢复的，这允许我们在同一器件上重复观察偏置应力和恢复特性。这项工作阐明了化学处理的 Pb 硫属化物 QD 薄膜中电荷输运的各个方面，与正在进行的将这些薄膜应用于光电设备的研究相关。
