School of Chemical Engineering and Material Science, Chung-Ang University, Seoul, 156-756, South Korea.
Phys Chem Chem Phys. 2013 Sep 21;15(35):14777-82. doi: 10.1039/c3cp52422a.
In this study, we attempt to unveil the charge-transport abnormality of the widely studied diketopyrrolopyrrole (DPP)-based polymers with exceptionally high charge carrier mobility [>5 cm(2) V(-1) s(-1)]. Based on the electric field and temperature dependence of the charge-transport characteristics of the field effect transistor (FET) geometry of one of the highly conductive DPP derivatives, namely, (poly[2,5-bis(7-decylnonadecyl)pyrrolo[3,4-c]pyrrole-1,4(2H,5H)-dione-(E)-(1,2-bis(5-(thiophen-2-yl)selenophen-2-yl)ethene) (PDPPDTSE), we show that the high gate-source bias drew the carriers closer to the interface of the semiconductor/dielectric layers where the density of state (DOS) of the charge carrier is significantly broader than the bulk. We argue that the intrinsically narrow DOS in the PDPPDTSE bulk resulted in significantly different charge-transport behavior between the semiconductor bulk and the semiconductor/dielectric interface, which was not visible in the other low-mobility organic semiconductors that contain intrinsically high density of trap states in their bulk. To avoid these charge transport abnormalities, we try to operate the FETs under low gate bias without compromising the accumulated charge carrier density. By carefully employing a thin metal oxide covered with a self-assembled monolayer (SAM) as a dielectric layer, we can demonstrate low-voltage PDPPDTSE FETs with near-ideal performance both in terms of hysteresis-free operation and operating reliability while maintaining a high charge carrier mobility of ~2.8 cm(2) V(-1) s(-1).
在这项研究中,我们试图揭示具有异常高电荷载流子迁移率[>5 cm(2) V(-1) s(-1)]的广泛研究的二酮吡咯并吡咯(DPP)基聚合物的电荷输运异常。基于场效应晶体管(FET)几何形状的一种高导电性 DPP 衍生物,即(聚[2,5-双(7-癸基十九烷基)吡咯并[3,4-c]吡咯-1,4(2H,5H)-二酮-(E)-(1,2-双(5-(噻吩-2-基)硒吩-2-基)乙烯)(PDPPDTSE)的电荷输运特性的电场和温度依赖性,我们表明高栅源偏压使载流子更接近半导体/介电层的界面,在该界面处电荷载流子的态密度(DOS)明显比体相宽。我们认为,PDPPDTSE 体相中固有的窄 DOS 导致了半导体体相和半导体/介电界面之间的电荷输运行为明显不同,而在其他包含体相中固有高密度陷阱态的低迁移率有机半导体中,这种行为并不明显。为了避免这些电荷输运异常,我们尝试在不降低累积电荷载流子密度的情况下在低栅极偏压下操作 FET。通过仔细使用覆盖有自组装单层(SAM)的薄金属氧化物作为介电层,我们可以证明 PDPPDTSE FET 在低电压下具有近乎理想的性能,无论是在无滞后操作还是在操作可靠性方面,同时保持约 2.8 cm(2) V(-1) s(-1)的高电荷载流子迁移率。