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导电桥接随机存取存储器:3D架构面临的挑战与机遇

Conductive-bridging random access memory: challenges and opportunity for 3D architecture.

作者信息

Jana Debanjan, Roy Sourav, Panja Rajeswar, Dutta Mrinmoy, Rahaman Sheikh Ziaur, Mahapatra Rajat, Maikap Siddheswar

机构信息

Thin Film Nano Tech. Lab., Department of Electronic Engineering, Chang Gung University, 259 Wen-Hwa 1st Rd., Kwei-Shan, Tao-Yuan 333 Taiwan.

Thin Film Nano Tech. Lab., Department of Electronic Engineering, Chang Gung University, 259 Wen-Hwa 1st Rd., Kwei-Shan, Tao-Yuan 333 Taiwan ; Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, 713 209 India.

出版信息

Nanoscale Res Lett. 2015 Apr 18;10:188. doi: 10.1186/s11671-015-0880-9. eCollection 2015.

Abstract

The performances of conductive-bridging random access memory (CBRAM) have been reviewed for different switching materials such as chalcogenides, oxides, and bilayers in different structures. The structure consists of an inert electrode and one oxidized electrode of copper (Cu) or silver (Ag). The switching mechanism is the formation/dissolution of a metallic filament in the switching materials under external bias. However, the growth dynamics of the metallic filament in different switching materials are still debated. All CBRAM devices are switching under an operation current of 0.1 μA to 1 mA, and an operation voltage of ±2 V is also needed. The device can reach a low current of 5 pA; however, current compliance-dependent reliability is a challenging issue. Although a chalcogenide-based material has opportunity to have better endurance as compared to an oxide-based material, data retention and integration with the complementary metal-oxide-semiconductor (CMOS) process are also issues. Devices with bilayer switching materials show better resistive switching characteristics as compared to those with a single switching layer, especially a program/erase endurance of >10(5) cycles with a high speed of few nanoseconds. Multi-level cell operation is possible, but the stability of the high resistance state is also an important reliability concern. These devices show a good data retention of >10(5) s at >85°C. However, more study is needed to achieve a 10-year guarantee of data retention for non-volatile memory application. The crossbar memory is benefited for high density with low power operation. Some CBRAM devices as a chip have been reported for proto-typical production. This review shows that operation current should be optimized for few microamperes with a maintaining speed of few nanoseconds, which will have challenges and also opportunities for three-dimensional (3D) architecture.

摘要

本文综述了基于不同开关材料(如硫族化物、氧化物和不同结构的双层材料)的导电桥接随机存取存储器(CBRAM)的性能。该结构由一个惰性电极和一个铜(Cu)或银(Ag)的氧化电极组成。开关机制是在外部偏压下,开关材料中金属细丝的形成/溶解。然而,不同开关材料中金属细丝的生长动力学仍存在争议。所有CBRAM器件都在0.1 μA至1 mA的工作电流下进行开关操作,并且还需要±2 V的工作电压。该器件可以达到5 pA的低电流;然而,与电流依从性相关的可靠性是一个具有挑战性的问题。尽管与氧化物基材料相比,硫族化物基材料有机会具有更好的耐久性,但数据保持以及与互补金属氧化物半导体(CMOS)工艺的集成也是问题。与具有单个开关层的器件相比,具有双层开关材料的器件表现出更好的电阻开关特性,尤其是具有大于10(5) 次循环的编程/擦除耐久性以及几纳秒的高速。多级单元操作是可行的,但高电阻状态的稳定性也是一个重要的可靠性问题。这些器件在高于85°C的温度下表现出大于10(5) 秒的良好数据保持能力。然而,要实现非易失性存储器应用的数据保持10年保证,还需要更多的研究。交叉开关存储器有利于实现高密度和低功耗操作。一些作为芯片的CBRAM器件已被报道用于原型生产。这篇综述表明,工作电流应优化至几微安,并保持几纳秒的速度,这对于三维(3D)架构来说既具有挑战也存在机遇。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/fcba/4412874/9acd4457cf3e/11671_2015_880_Fig1_HTML.jpg

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