基于Elitestek Ti60现场可编程门阵列的高精度时间数字转换器设计。

Design of a high-precision time-to-digital converter in an Elitestek Ti60 field-programmable-gate-array.

作者信息

He Zongwu, Wen Xincheng, Wang Jian, Ma Qingli, Yin Zejie

机构信息

State Key Laboratory of Particle Detection and Electronics, Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China.

Deep Space Exploration Laboratory, Hefei 230088, China.

出版信息

Rev Sci Instrum. 2024 Aug 1;95(8). doi: 10.1063/5.0220494.

DOI:10.1063/5.0220494

PMID:39166914

Abstract

The time-to-digital converter (TDC) implemented in a field-programmable-gate-array has garnered widespread attention due to its flexibility and high-performance capabilities. However, issues such as non-uniformity, the bubble in the tapped delay line, and the presence of certain ultra-wide delay units can significantly compromise the precision and nonlinearity of the TDC. In this paper, we propose a high-precision TDC in an Elitestek Ti60 FPGA, effectively eliminating the adverse effects of non-uniformity, the bubble, and certain ultra-wide delay units. The TDC is constructed with a 318-stage delay chain and operates at a low system clock frequency of 150 MHz. The least significant bit (LSB) of the TDC is 21.92 ps. The differential nonlinearity (DNL) is between (-0.976, 1.615) LSB and the integral nonlinearity (INL) is between (-1.446, 2.678) LSB. The TDC achieves a root-mean-square error of 14.783 ps when utilized for measuring various time intervals.

摘要

在现场可编程门阵列中实现的时间数字转换器（TDC）因其灵活性和高性能而受到广泛关注。然而，诸如不均匀性、抽头延迟线中的气泡以及某些超宽延迟单元的存在等问题，会显著影响TDC的精度和非线性。在本文中，我们在Elitestek Ti60 FPGA中提出了一种高精度TDC，有效消除了不均匀性、气泡和某些超宽延迟单元的不利影响。该TDC由一个318级延迟链构成，工作在150 MHz的低系统时钟频率下。TDC的最低有效位（LSB）为21.92 ps。微分非线性（DNL）在（-0.976, 1.615）LSB之间，积分非线性（INL）在（-1.446, 2.678）LSB之间。当用于测量各种时间间隔时，该TDC实现了14.783 ps的均方根误差。