Note: All-digital pulse-shrinking time-to-digital converter with improved dynamic range.

This paper proposes an all-digital pulse-shrinking time-to-digital converter (TDC) using the offset error cancellation circuitry to widen its dynamic range and to improve its accuracy. Although the TDC based on a pulse-shrinking mechanism can achieve a sub-gate resolution without circuit complexity, it possesses an undesired offset error that results in a nonzero lower bound appeared in its dynamic range and then affects its accuracy. The proposed cancellation circuitry for eliminating the offset error consists of a time adder with a delay line and a time subtractor with an identical delay line. The experimental TDC is implemented on Xilinx field programmable gate arrays and it also functions successfully in improving its dynamic range.