一种基于7.4皮秒现场可编程门阵列且带有1024单元测量矩阵的时间数字转换器。
A 7.4 ps FPGA-Based TDC with a 1024-Unit Measurement Matrix.
作者信息
Zhang Min, Wang Hai, Liu Yan
机构信息
School of Electro-Mechanical Engineering, Xidian University, Xi'an 710071, China.
School of Aerospace Science and Technology, Xidian University, Xi'an 710071, China.
出版信息
Sensors (Basel). 2017 Apr 14;17(4):865. doi: 10.3390/s17040865.
In this paper, a high-resolution time-to-digital converter (TDC) based on a field programmable gate array (FPGA) device is proposed and tested. During the implementation, a new architecture of TDC is proposed which consists of a measurement matrix with 1024 units. The utilization of routing resources as the delay elements distinguishes the proposed design from other existing designs, which contributes most to the device insensitivity to variations of temperature and voltage. Experimental results suggest that the measurement resolution is 7.4 ps, and the INL (integral nonlinearity) and DNL (differential nonlinearity) are 11.6 ps and 5.5 ps, which indicates that the proposed TDC offers high performance among the available TDCs. Benefitting from the FPGA platform, the proposed TDC has superiorities in easy implementation, low cost, and short development time.
本文提出并测试了一种基于现场可编程门阵列（FPGA）器件的高分辨率时间数字转换器（TDC）。在实现过程中，提出了一种新的TDC架构，它由一个包含1024个单元的测量矩阵组成。将路由资源用作延迟元件的做法使该设计有别于其他现有设计，这对器件对温度和电压变化的不敏感性贡献最大。实验结果表明，测量分辨率为7.4 ps，积分非线性（INL）和微分非线性（DNL）分别为11.6 ps和5.5 ps，这表明所提出的TDC在现有TDC中具有高性能。受益于FPGA平台，所提出的TDC在易于实现、低成本和短开发时间方面具有优势。
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