一种采用新型波形合并方法的尺寸、重量、功耗和成本高效的32通道时间数字转换器。

A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method.

作者信息

Alshahry Saleh M, Alshehry Awwad H, Alhazmi Abdullah K, Chodavarapu Vamsy P

机构信息

Department of Electrical and Computer Engineering, University of Dayton, 300 College Park, Dayton, OH 45469, USA.

出版信息

Sensors (Basel). 2023 Jul 23;23(14):6621. doi: 10.3390/s23146621.

DOI:10.3390/s23146621

PMID:37514914

原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC10384146/

Abstract

We present a Tapped Delay Line (TDL)-based Time to Digital Converter (TDC) using Wave Union type A (WU-A) architecture for applications that require high-precision time interval measurements with low size, weight, power, and cost (SWaP-C) requirements. The proposed TDC is implemented on a low-cost Field-Programmable Gate Array (FPGA), Artix-7, from Xilinx. Compared to prior works, our high-precision multi-channel TDC has the lowest SWaP-C requirements. We demonstrate an average time precision of less than 3 ps and a Root Mean Square resolution of about 1.81 ps. We propose a novel Wave Union type A architecture where only the first multiplexer is used to generate the wave union pulse train at the arrival of the start signal to minimize the required computational processing. In addition, an auto-calibration algorithm is proposed to help improve the TDC performance by improving the TDC Differential Non-Linearity and Integral Non-Linearity.

摘要

我们展示了一种基于抽头延迟线（TDL）的时间数字转换器（TDC），它采用波合并A（WU-A）型架构，适用于对尺寸、重量、功耗和成本（SWaP-C）有要求的高精度时间间隔测量应用。所提出的TDC在赛灵思公司低成本的现场可编程门阵列（FPGA）Artix-7上实现。与先前的工作相比，我们的高精度多通道TDC具有最低的SWaP-C要求。我们展示了小于3 ps的平均时间精度和约1.81 ps的均方根分辨率。我们提出了一种新颖的波合并A型架构，其中仅使用第一个多路复用器在起始信号到达时生成波合并脉冲序列，以最小化所需的计算处理。此外，还提出了一种自动校准算法，通过改善TDC的差分非线性和积分非线性来帮助提高TDC性能。