Materials Science and Engineering Program, University of California, Riverside, CA 92521 USA.
Department of Electrical and Comp. Engineering, University of California, Riverside, CA 92521 USA.
Sci Rep. 2017 Feb 10;7:41593. doi: 10.1038/srep41593.
Silicon nitride stress capping layer is an industry proven technique for increasing electron mobility and drive currents in n-channel silicon MOSFETs. Herein, the strain induced by silicon nitride is firstly characterized through the changes in photoluminescence and Raman spectra of a bare bilayer MoS (Molybdenum disulfide). To make an analogy of the strain-gated silicon MOSFET, strain is exerted to a bilayer MoS field effect transistor (FET) through deposition of a silicon nitride stress liner that warps both the gate and the source-drain area. Helium plasma etched MoS layers for edge contacts. Current on/off ratio and other performance metrics are measured and compared as the FETs evolve from back-gated, to top-gated and finally, to strain-gated configurations. While the indirect band gap of bilayer MoS at 0% strain is 1.25 eV, the band gap decreases as the tensile strain increases on an average of ~100 meV per 1% tensile strain, and the decrease in band gap is mainly due to lowering the conduction band at K point. Comparing top- and strain-gated structures, we find a 58% increase in electron mobility and 46% increase in on-current magnitude, signalling a benign effect of tensile strain on the carrier transport properties of MoS.
氮化硅应力覆盖层是一种经过行业验证的技术，可提高 n 通道硅 MOSFET 中的电子迁移率和驱动电流。在此，通过裸双层 MoS（二硫化钼）的光致发光和拉曼光谱的变化，首先对氮化硅引起的应变进行了表征。为了类比应变栅硅 MOSFET，通过沉积氮化硅应力气垫来对双层 MoS 场效应晶体管（FET）施加应变，从而使栅极和源漏区变形。使用氦等离子体刻蚀 MoS 层以形成边缘接触。随着 FET 从背栅极、顶栅极最终变为应变栅极，测量并比较了电流导通/关断比和其他性能指标。当双层 MoS 在 0%应变时的间接带隙为 1.25 eV 时，随着拉伸应变的增加，带隙平均每增加 1%拉伸应变约降低 100 meV，带隙的降低主要归因于 K 点导带的降低。比较顶栅极和应变栅极结构，我们发现电子迁移率增加了 58%，导通电流幅度增加了 46%，这表明拉伸应变对 MoS 的载流子输运性能有良性影响。
