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消除全二维栅极堆叠负电容晶体管中的铁电滞回现象。

Eliminating Ferroelectric Hysteresis in All-Two-Dimensional Gate-Stack Negative-Capacitance Transistors.

作者信息

Quan Hui, Meng Dehuan, Ma Xuezhou, Qiu Chenguang

机构信息

Hunan Institute of Advanced Sensing and Information Technology, Xiangtan University, Xiangtan 411105, China.

Key Laboratory for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, School of Electronics, Peking University, Beijing 100871, China.

出版信息

ACS Appl Mater Interfaces. 2023 Sep 27;15(38):45076-45082. doi: 10.1021/acsami.3c06161. Epub 2023 Sep 18.

DOI:10.1021/acsami.3c06161
PMID:37721972
Abstract

Boltzmann distribution thermal tails of carriers restrain the subthreshold swing (SS) of field-effect transistors (FETs) to be lower than 60 mV/decade at room temperature, which restrains the reduction of operate-voltage and power consumption of transistors. The negative-capacitance FET (NC FET) is expected to break through this physical limit and obtain a steep SS by amplifying the gate voltage through the negative capacitance effect of the ferroelectric thin film, providing a new way to further reduce the power consumption of the transistor at the end of Moore's law. Here, we show a MoS NC FET with a CuInPS ferroelectric, exhibiting a large on/off ratio of 10, a steep SS as low as 6 mV/decade, and a wide sub-60 mV/decade drain current range of more than 4 orders of magnitude while sacrificially inducing a huge hysteresis larger than 500 mV. Furthermore, we found that by inserting the h-phase boron nitride (h-BN) layer with suitable thickness, the dielectric capacitance matches the ferroelectric negative capacitance better, and thus the hysteresis on the transfer curve is reduced, and the ideal switching-behavior transistors with SS as low as 62 mV/decade and only 5 mV negligible hysteresis were obtained. Our work demonstrates that under the capacitance-matching condition, the hysteresis-free negative-capacitance transistors do not act as the predicted steep-slope transistors, but their voltage-saving still occurs instead as a type of effective transconductance booster with more than 20 times transconductance amplification.

摘要

玻尔兹曼分布的载流子热尾使得场效应晶体管(FET)在室温下的亚阈值摆幅(SS)低于60 mV/十倍频程,这限制了晶体管工作电压和功耗的降低。负电容FET(NC FET)有望突破这一物理极限,通过铁电薄膜的负电容效应放大栅极电压来获得陡峭的SS,为在摩尔定律末期进一步降低晶体管功耗提供了新途径。在此,我们展示了一种具有CuInPS铁电体的MoS NC FET,其开/关比高达10,SS低至6 mV/十倍频程,并且在牺牲性地诱导出大于500 mV的巨大滞后的情况下,具有超过4个数量级的宽亚60 mV/十倍频程漏极电流范围。此外,我们发现通过插入具有合适厚度的h相氮化硼(h-BN)层,介电电容与铁电负电容匹配得更好,从而降低了转移曲线上的滞后,并且获得了理想的开关行为晶体管,其SS低至62 mV/十倍频程且滞后仅为5 mV可忽略不计。我们的工作表明,在电容匹配条件下,无滞后的负电容晶体管并不像预测的陡坡晶体管那样工作,但其电压节省仍然会发生,而是作为一种跨导放大超过20倍的有效跨导增强器。

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