Lee Chang-Chun, Tzeng Tzai-Liang, Huang Pei-Chen
Department of Mechanical Engineering, Research Center for Microsystem Engineering, Chung Yuan Christian University, 200 Chung Pei Road, Chung Li District, Taoyuan City 32023, Taiwan.
Materials (Basel). 2015 Aug 7;8(8):5121-5137. doi: 10.3390/ma8085121.
three-dimensional integrated circuit (3D-IC) structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF). The mechanical properties of this equivalent material, including Young's modulus (E), Poisson's ratio, shear modulus, and coefficient of thermal expansion (CTE), are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture.
具有显著尺寸失配的三维集成电路（3D-IC）结构会给解析模型构建带来困难。本文提出一种模拟技术，引入一种由微凸块及其周围晶圆级底部填充胶（WLUF）组成的等效材料。通过分别施加拉伸载荷或恒定位移以及在模拟过程中升高温度，直接获得该等效材料的力学性能，包括杨氏模量（E）、泊松比、剪切模量和热膨胀系数（CTE）。分析结果表明，为了在相关区域获得准确的应力/应变轮廓，芯片堆叠结构最外层区域至少需要考虑八个微凸块。此外，还提出了一种带有方差分析的析因实验设计，以通过芯片厚度、基板厚度、CTE和E值这四个因素来优化芯片堆叠结构的可靠性。分析结果表明，最显著的因素是WLUF的CTE。该因素会影响温度循环载荷和高温键合过程下微凸块的可靠性和结构翘曲。建议使用低CTE和高E值的WLUF来提高3D-IC架构的组装可靠性。
